Patent ReferencesSelf-aligning integrated circuit assembly Polysilicon FETs Semiconductor device Sidewall doping technique for SOI transistors SOI type vertical channel field effect transistor and process of manufacturing the same Patent #: 5312782 InventorAssigneeApplicationNo. 145268 filed on 10/29/1993US Classes:257/717, Isolation of cooling means (e.g., heat sink) by an electrically insulating element (e.g., spacer)257/347, Single crystal semiconductor layer on insulating substrate (SOI)257/713, For integrated circuit257/E23.105Wire-like or pin-like cooling fins or heat sinks (EPO)ExaminersPrimary: Ostrowski, DavidAttorney, Agent or FirmInternational ClassH01L 023/34AbstractA heat sink is formed on a bonded semiconductor on insulator (SOI) wafer. A trench is formed which extends from a top of the bonded SOI wafer through an isolation region of the bonded SOI wafer to a base of the bonded SOI wafer. The base of the bonded SOI wafer is located below the isolation region of the bonded SOI wafer. A conductive pillar is formed in the trench. The conductive pillar extends from the top of the bonded SOI wafer through the isolation region of the bonded SOI wafer and is physically in contact with but electrically insulated from the base of the bonded SOI wafer. In the preferred embodiment, the conductive pillar is formed of doped polysilicon. The doped polysilicon is of a conductivity type which is different than the conductivity type of the base. Out-diffusion from the doped polysilicon forms a region within the base which electrically insulates the conductive pillar from the base.Other References
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