High frequency noise and impedance matched integrated circuits
Patent 5789799 Issued on August 4, 1998. Estimated Expiration Date: 
September 27, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 27, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesHeterodyne stage having precise closed-loop control of the amplitude of the injection signal thereof VHF DC-DC power supply operating at frequencies greater than 50 MHz Two-port wideband bipolar transistor amplifiers Patent #: 5164682 InventorsAssigneeApplicationNo. 727367 filed on 09/27/1996US Classes:257/578, With enlarged emitter area (e.g., power device)257/565, BIPOLAR TRANSISTOR STRUCTURE257/567, Darlington configuration (i.e., emitter to collector current of input transistor supplied to base region of output transistor)257/568, More than two Darlington-connected transistors257/569, Complementary Darlington-connected transistors257/570With active components in addition to Darlington transistors (e.g., antisaturation diode, bleeder diode connected antiparallel to input transistor base-emitter junction, etc.)ExaminersPrimary: Whitehead, Carl Jr.Attorney, Agent or FirmInternational ClassH01L 027/082AbstractAn monolithic integrated circuit comprising a transistor-inductor structure is provided having simultaneously noise matched and input impedance matched characteristics at a desired frequency. The transistor-inductor structure comprises a first transistor Q1 which may be a common emitter bipolar transistor or common source MOSFET transistor Q1, a second optional transistor Q2, a first inductor LE in the emitter (source) of Q1, and a second inductor LB in the base (gate) of Q1. The emitter length lE1, or correspondingly the gate width wg, of Q1 is designed such that the real part of its optimum noise impedance is equal to the characteristic impedance of the system, Z0, which is typically 50Ω. The first inductor LE, provides matching of the real part of the input impedance and the second inductor LB cancels out the noise reactance and input impedance reactance of the structure. The resulting simultaneously noise and impedance matched integrated circuit provides optimal performance. The optimized transistor-inductor structure has particular application to silicon integrated circuits, such as low noise amplifiers and mixer circuits, for wireless and RF circuit applications at 5.8 Ghz, previously reported only for GaAs based circuits. Other basic silicon integrated circuits were optimized at frequencies up to ~12 GHz.Other References
Field of SearchWith enlarged emitter area (e.g., power device)Including inductive element BIPOLAR TRANSISTOR STRUCTURE Plural non-isolated transistor structures in same structure Darlington configuration (i.e., emitter to collector current of input transistor supplied to base region of output transistor) More than two Darlington-connected transistors Complementary Darlington-connected transistors With active components in addition to Darlington transistors (e.g., antisaturation diode, bleeder diode connected antiparallel to input transistor base-emitter junction, etc.) WITH PASSIVE COMPONENTS, (e.g., POLYSILICON RESISTORS) Variable conversion efficiency (variable oscillator amplitude, etc.) Having transistorized inverter By semiconductor rectifier and inverter Double-ended (i.e., push-pull), self-oscillating type Double-ended (i.e., push-pull), separately-driven type | |
