Single poly memory cell and array
September 18, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3846768 Method and apparatus for addressing a non-volatile memory array Addressable MNOS cell for non-volatile memories Non-volatile memory with improved readout Semiconductor memory device Method of forming an array of non-volatile sonos memory cells and array of non-violatile sonos memory cells Array of non-volatile sonos memory cells Grounded memory core for Roms, Eproms, and EEpproms having an address decoder, and sense amplifier Field shield isolated EPROM Flash memory system, and methods of constructing and utilizing same Patent #: 5656837 InventorsAssigneeApplicationNo. 715569 filed on 09/18/1996US Classes:257/296, Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell)257/324, Multiple insulator layers (e.g., MNOS structure)257/E21.679, Charge trapping insulator nonvolatile memory structures (EPO)257/E27.103Electrically programmable ROM (EPO)ExaminersPrimary: Meier, Stephen D.Attorney, Agent or FirmInternational ClassesH01L 027/108H01L 029/76 H01L 029/94 H01L 031/119 AbstractA non-volatile memory cell array using only a single level of polysilicon and a single level of metal has programmable single transistor memory cells on a semiconductor substrate of a first conductivity type, a well of a second conductivity type in the substrate, parallel bitlines oriented in a first direction, and reference line segments oriented in the first direction. Each reference line is paired with one of each bitline. The array also has parallel word lines oriented in a second direction to form an array of intersections with the pairs of bitline/reference line pairs, and a rewriteable single transistor memory cell at each intersection point.Field of SearchMultiple insulator layers (e.g., MNOS structure)Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device) Combined with heavily doped channel stop portion Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell) | |
