Reconfigurable computer architecture for use in signal processing applications
May 28, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesVersatile and efficient cell-to-local bus interface in a configurable logic array Virtual processor module including a reconfigurable programmable matrix Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor Programmable logic module and architecture for field programmable gate array device System and method for dynamically reconfiguring a programmable gate array FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions Patent #: 5684980 InventorApplicationNo. 654395 filed on 05/28/1996US Classes:712/37, Programmable (e.g., EPROM)712/22, Single instruction, multiple data (SIMD)712/23, Superscalar712/43, Mode switching712/200ARCHITECTURE BASED INSTRUCTION PROCESSINGExaminersPrimary: Donaghue, Larry D.Attorney, Agent or FirmInternational ClassG06F 015/00AbstractAn architecture for information processing devices which allows the construction of low cost, high performance systems for specialized computing applications involving sensor data processing. The reconfigurable processor architecture of the invention uses a programmable logic structure called an Adaptive Logic Processor (ALP). This structure is similar to an extendible field programmable gate array (FPGA) and is optimized for the implementation of program specific pipeline functions, where the function may be changed any number of times during the progress of a computation. A Reconfigurable Pipeline Instruction Control (RPIC) unit is used for loading the pipeline functions into the ALP during the configuration process and coordinating the operations of the ALP with other information processing structures, such as memory, I/O devices, and arithmetic processing units. Multiple components having the reconfigurable architecture of the present invention may be combined to produce high performance parallel processing systems based on the Single Instruction Multiple Data (SIMD) architecture concept.Other References
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