Method of frabricating a MOS transistor having a composite gate electrode
April 29, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMOS Integrated circuit having refractory metal or metal silicide interconnect layer Method of producing titanium nitride MOS device gate electrode Semiconductor integrated circuit device Polycide process for integrated circuits Composite inverse T-gate metal oxide semiconductor device and method of fabrication Process for etching Etchback process for tungsten contact/via filling Method for forming a thick base oxide in a BiCMOS process Semiconductor device of MOS structure having p-type gate electrode Process for plasma etching Patent #: 5236549 InventorsApplicationNo. 639776 filed on 04/29/1996US Classes:438/592, Possessing plural conductive layers (e.g., polycide)257/E21.201, Conductor layer next to insulator is Si or Ge or C and their non-Si alloys (EPO)257/E21.202, Conductor layer next to the insulator is single metal, e.g., Ta, W, Mo, Al (EPO)257/E21.203, Conductor layer next to insulator is metallic silicide (Me Si) (EPO)257/E21.204, Conductor layer next to insulator is non-MeSi composite or compound, e.g., TiN (EPO)257/E21.435, Lateral single gate single channel silicon transistor with both lightly doped source and drain extensions and source and drain self-aligned to sides of gate, e.g., LDD MOSFET, DDD MOSFET (EPO)257/E29.158, Elemental metal gate conductor material (e.g., W, Mo) (EPO)257/E29.16, Gate conductor material being compound or alloy material (e.g., organic material, TiN, MoSi 2 ) (EPO)257/E29.161, Silicide (EPO)257/E29.255, With field effect produced by insulated gate (EPO)438/303, Utilizing gate sidewall structure438/307Using same conductivity-type dopantExaminersPrimary: Trinh, MichaelAttorney, Agent or FirmForeign Patent References
International ClassH01L 021/320.5AbstractA novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite gate electrode is formed on a gate insulating layer which is formed on a silicon substrate. A pair of source/drain regions are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode. | |
