A method of swing on a swing is disclosed, in which a user positioned on a standard swing suspended by two chains from a substantially horizontal tree branch induces side to side motion by pulling alternately on one chain and then the other.
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AbstractA novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite gate electrode is formed on a gate insulating layer which is formed on a silicon substrate. A pair of source/drain regions are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode. | InventorsApplicationNo. 639776 filed on 04/29/1996US Classes:438/592, Possessing plural conductive layers (e.g., polycide)257/E21.201, Conductor layer next to insulator is Si or Ge or C and their non-Si alloys (EPO)257/E21.202, Conductor layer next to the insulator is single metal, e.g., Ta, W, Mo, Al (EPO)257/E21.203, Conductor layer next to insulator is metallic silicide (Me Si) (EPO)257/E21.204, Conductor layer next to insulator is non-MeSi composite or compound, e.g., TiN (EPO)257/E21.435, Lateral single gate single channel silicon transistor with both lightly doped source and drain extensions and source and drain self-aligned to sides of gate, e.g., LDD MOSFET, DDD MOSFET (EPO)257/E29.158, Elemental metal gate conductor material (e.g., W, Mo) (EPO)257/E29.16, Gate conductor material being compound or alloy material (e.g., organic material, TiN, MoSi 2 ) (EPO)257/E29.161, Silicide (EPO)257/E29.255, With field effect produced by insulated gate (EPO)438/303, Utilizing gate sidewall structure438/307Using same conductivity-type dopantField of Search438/592, Possessing plural conductive layers (e.g., polycide)438/303, Utilizing gate sidewall structure438/307Using same conductivity-type dopantExaminersPrimary: Trinh, MichaelAttorney, Agent or FirmUS Patent References4392150, MOS Integrated circuit having refractory metal or metal silicide interconnect layerIssued on: 07/05/1983 Inventor: Courreges4570328, Method of producing titanium nitride MOS device gate electrode Issued on: 02/18/1986 Inventor: Price , et al.4717684, Semiconductor integrated circuit device Issued on: 01/05/1988 Inventor: Katto , et al.4816425, Polycide process for integrated circuits Issued on: 03/28/1989 Inventor: McPherson5097301, Composite inverse T-gate metal oxide semiconductor device and method of fabrication Issued on: 03/17/1992 Inventor: Sanchez5110408, Process for etching Issued on: 05/05/1992 Inventor: Fujii, et al.5167760, Etchback process for tungsten contact/via filling Issued on: 12/01/1992 Inventor: Mu, et al.5171702, Method for forming a thick base oxide in a BiCMOS process Issued on: 12/15/1992 Inventor: Prengle, et al.5189504, Semiconductor device of MOS structure having p-type gate electrode Issued on: 02/23/1993 Inventor: Nakayama, et al.5236549Process for plasma etching Issued on: 08/17/1993 Inventor: Shirakawa, et al. Foreign Patent References
International ClassH01L 021/320.5 |