Table based data speculation circuit for parallel processing computer
Patent 5781752 Issued on July 14, 1998. Estimated Expiration Date: 
December 26, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 26, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesApparatus for handling out-of-order exceptions in pipe-lined parallel processing that prevents execution of all instructions behind exception predicted instruction and aborts if exception actually occurs Apparatus to dynamically control the out-of-order execution of load/store instructions in a processor capable of dispatchng, issuing and executing multiple instructions in a single processor cycle Patent #: 5666506 InventorsAssigneeApplicationNo. 773992 filed on 12/26/1996US Classes:712/216DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTIONExaminersPrimary: Lim, KrisnaAttorney, Agent or FirmInternational ClassG06F 009/38AbstractA predictor circuit permits advanced execution of instructions depending for their data on previous instructions by predicting such dependencies based on previous mis-speculations detected at the final stages of processing. Synchronization of dependent instructions is provided by a table creating entries for each instance of potential dependency. Table entries are created and deleted dynamically to limit total memory requirements.Other References
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