U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Icon_funbox Bizarre Patents

Patent No. 6266829

Combination Beverage Container and Spittoon

A combination beverage container and spittoon includes a bottom portion including outer wall and a first inner wall defining a spittoon space.

Newsletter  PatentStorm News

Make the Most of PatentStorm

See this month's Top Inventors and Most Cited Patents.

Stay on top of the latest patents by subscribing to an RSS feed.

Got questions? Ask a Patent Expert!

Registered users: Manage your profile, comments and alerts.

 

US Patent 5781752 - Table based data speculation circuit for parallel processing computer

US Patent Issued on July 14, 1998
Estimated Patent Expiration Date: Icon_subject December 26, 2016Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
loading...


View Patent Images (PDF)
(Registered users only)

Abstract

A predictor circuit permits advanced execution of instructions depending for their data on previous instructions by predicting such dependencies based on previous mis-speculations detected at the final stages of processing. Synchronization of dependent instructions is provided by a table creating entries for each instance of potential dependency. Table entries are created and deleted dynamically to limit total memory requirements.

Other References

  • Gurinda Sohi et al., Instruction Issue Logic for High-Performance Interruptable Pipelined Processors; ACM 1987, pp. 27-3

Inventors

Assignee

Application

No. 773992 filed on 12/26/1996

US Classes:

712/216DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION

Examiners

Primary: Lim, Krisna

Attorney, Agent or Firm

US Patent References

5664138, Apparatus for handling out-of-order exceptions in pipe-lined parallel processing that prevents execution of all instructions behind exception predicted instruction and aborts if exception actually occurs
Issued on: 09/02/1997
Inventor: Yoshida
5666506Apparatus to dynamically control the out-of-order execution of load/store instructions in a processor capable of dispatchng, issuing and executing multiple instructions in a single processor cycle
Issued on: 09/09/1997
Inventor: Hesson, et al.

International Class

G06F 009/38

Comments

No comments for this page
 
 
Forgot password?
Register here