System and method for reducing errors in a delta-sigma converter
Patent 5781137 Issued on July 14, 1998. Estimated Expiration Date: 
December 23, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 23, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesA/D converter including error correction for a local D/A converter Patent #: 5101205 InventorAssigneeApplicationNo. 771480 filed on 12/23/1996US Classes:341/118, CONVERTER COMPENSATION341/143Differential encoder and/or decoder (e.g., delta modulation, differential pulse code modulation)ExaminersPrimary: Young, BrianAttorney, Agent or FirmInternational ClassH03M 001/06AbstractA system and method for reducing linearity errors in a delta-sigma converter. The linearity errors in the delta-sigma converter are modeled by generating a set of digital signals representative of an inputted sine wave. The set of digital signals are low-pass filtered and subjected to a fast Fourier transform algorithm to generate a frequency domain representation of the sine wave. Thereafter, a net linearity error spectrum is removed from the frequency domain representation and inverse Fourier transform back into the time domain. The filtered set of digital signals are also sorted into subsets of digital signals where each signal in a subset corresponds to a particular output of a delta-sigma modulator contained within the delta-sigma converter. A fast Fourier transform algorithm is applied to each of the filtered subsets of digital signals to generate a frequency domain representation thereof. Specific linearity errors are generated by applying an inverse Fourier transform algorithm to each of the specific linearity error spectrums in the frequency domain representations of the filtered subsets of digital signals. Thereafter, linearity error correction coefficients are generated as a function of the net linearity error and the specific linearity errors. The linearity error correction coefficients are used to generate entries in a look-up table where the entries are adjustable by digital outputs of the delta-sigma modulator. The look-up table is used to correct digital signals outputted by the delta-sigma modulator prior to decimation and digital filter.Other References
Field of SearchCONVERTER COMPENSATIONCONVERTER CALIBRATION OR TESTING Temperature compensation Analog to digital conversion Differential encoder and/or decoder (e.g., delta modulation, differential pulse code modulation) Linearization (e.g., nonlinear transfer characteristic compensates for nonlinear transducer) | |
