Method for fabricating dielectric films for non-volatile electrically erasable memories
December 5, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod for forming an insulating layer on a polycrystalline silicon layer of a semiconductor device using a two-step thermal oxidation technique Method of making a floating gate memory cell Memory device with interconnected polysilicon layers and method for making Method of making devices having thin dielectric layers Elasticized gusseted dish cover, method of making same and article of dispensing Method of fabricating a textured tunnel oxide for EEPROM applications Method for forming concurrent top oxides using reoxidized silicon in an EPROM Patent #: 5665620 InventorAssigneeApplicationNo. 760474 filed on 12/05/1996US Classes:438/260, Textured surface of gate insulator or gate electrode257/E21.193, On single crystalline silicon (EPO)257/E21.285, Of silicon (EPO)438/585, Insulated gate formation438/594, Tunnelling dielectric layer438/770OxidationExaminersPrimary: Bowers, Charles L. Jr.Assistant: Whipple, Matthew Attorney, Agent or FirmInternational ClassH01L 021/316AbstractA method for forming a high-performance oxide as a tunneling dielectric for non-volatile memory applications. A silicon film containing amorphous silicon and good crystalline silicon micrograins is deposited in a silicon substrate by a LPCVD system. Then, a oxidation is performed at a temperature selected in a range such that non-uniform epitaxial silicon growth occurs at the silicon substrate. During an initial thermal oxidation process, the amorphous silicon region is quickly oxidized to form SiO2 and the good-crystalline silicon micrograins are also quickly oxidized to form the silicon-rich SiO2 (TOAS). In a following oxidation process, silicon precipitates are formed at the silicon-enriched region and the non-uniform epitaxial silicon growth is also enhanced at the silicon-enriched region. The enhanced non-uniformed silicon growth creates mild microtips. The silicon precipitates connect to the mild silicon microtips. Subsequently during the oxidation the ultra-high and sharp microtips are formed.Field of SearchTextured surface of gate insulator or gate electrodeTunneling insulator Tunneling insulator Oxidation Gate insulator structure constructed of plural layers or nonsilicon containing compound Tunnelling dielectric layer Insulated gate formation ELECTRON EMITTER MANUFACTURE DIFFERENTIAL OXIDATION AND ETCHING | |
