Method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time
January 11, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod and apparatus for scheduling the dispatch of instructions from a reservation station Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution Apparatus for pipeline streamlining where resources are immediate or certainly retired Circuit and method for scheduling instructions by predicting future availability of resources required for execution System for handling load and/or store operations in a superscalar microprocessor Patent #: 5557763 InventorsApplicationNo. 585361 filed on 01/11/1996US Classes:712/218, Commitment control or register bypass712/23, Superscalar712/215, Simultaneous issuance of multiple instructions712/216DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTIONExaminersPrimary: Treat, William M.Attorney, Agent or FirmInternational ClassG06F 009/38AbstractA method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time allows components within the processor to begin the steps of dispatch and execution of operations based on the speculated return of data for the operations at a predetermined time. After these steps have begun for an operation, a signal is received by one or more of these components if the operation cannot be completed at the speculated time. If the operation cannot be completed at the speculated time then the operation is canceled, recovering the state of the operation prior to the beginning of the steps of dispatch and execution.Other References
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