Method for forming EEPROM with split gate source side injection
Patent 5776810 Issued on July 7, 1998. Estimated Expiration Date: 
July 7, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
July 7, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References Re32401 High density N-channel silicon gate read only memory Method of making a high density floating gate electrically programmable ROM High density floating gate electrically programmable ROM Quaternary FET read only memory High density N-channel silicon gate read only memory Self-limiting erasable memory cell with triple level polysilicon Three layer floating gate memory transistor with erase gate over field oxide region Electrically alterable double dense memory Semiconductor RAM that is accessible in magnetic disc storage format InventorsAssigneeApplicationNo. 193707 filed on 02/09/1994US Classes:438/258, Including additional field effect transistor (e.g., sense or access transistor, etc.)257/E27.103, Electrically programmable ROM (EPO)257/E29.129, Gate electrodes for transistors with floating gate (EPO)257/E29.306, Hot carrier injection from channel (EPO)438/262, Including elongated source or drain region disposed under thick oxide regions (e.g., buried or diffused bitline, etc.)438/264, Tunneling insulator438/267Including forming gate electrode as conductive sidewall spacer to another electrodeExaminersPrimary: Trinh, MichaelAttorney, Agent or FirmForeign Patent References
International ClassH01L 021/336AbstractNovel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.Other References
Field of SearchIncluding additional field effect transistor (e.g., sense or access transistor, etc.)Including elongated source or drain region disposed under thick oxide regions (e.g., buried or diffused bitline, etc.) Tunneling insulator Including forming gate electrode as conductive sidewall spacer to another electrode | |
