Single merging bit DC-suppressed run length limited coding

Patent 5774078 Issued on June 30, 1998. Estimated Expiration Date:

April 5, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Method and apparatus for encoding and recovering binary digital data
Patent #: 4323931
Issued on: 04/06/1982
Inventor: Jacoby

Method of coding binary data
Patent #: 4501000
Issued on: 02/19/1985
Inventor: Immink , et al.

PCM signal transmission system
Patent #: 4703494
Issued on: 10/27/1987
Inventor: Ozaki , et al.

Method and apparatus for encoding binary data
Patent #: 4728929
Issued on: 03/01/1988
Inventor: Tanaka

Data processing apparatus
Patent #: 4833471
Issued on: 05/23/1989
Inventor: Tokuume , et al.

Data converting apparatus
Patent #: 5151699
Issued on: 09/29/1992
Inventor: Moriyama

Digital modulating apparatus and digital demodulating apparatus
Patent #: 5155485
Issued on: 10/13/1992
Inventor: Sako, et al.

Optical recording medium having thin protective layer and two-dimensionally aligned code words and recording/reproducing apparatus employing the same
Patent #: 5276674
Issued on: 01/04/1994
Inventor: Tanaka

Information recording method and optical disk apparatus using same
Patent #: 5333126
Issued on: 07/26/1994
Inventor: Fukuda, et al.

Encoding apparatus for digital signal with improved block channel coding Patent #: 5365231
Issued on: 11/15/1994
Inventor: Niimura

Inventors

Assignee

Application

No. 628167 filed on 04/05/1996

US Classes:

341/68, To or from NRZ (nonreturn-to-zero) codes341/59To or from run length limited codes

Examiners

Primary: Williams, Howard L.

Attorney, Agent or Firm

Greenblum & Bernstein, P.L.C.

Foreign Patent References

0178813 EP. 04/13/1986
0193153 EP. 09/13/1986
0347934 EP. 12/13/1989
0415853 EP. 03/13/1991
0511498 EP. 11/13/1992
0545516 EP. 06/13/1993
0577402 EP. 01/13/1994
0597443 EP. 05/13/1994
0625828 EP. 11/13/1994
0673029 EP. 09/13/1995
4304267 DE. 08/13/1993
63-56610 JP. 05/13/1983
60-114053 JP. 06/13/1985
60-106254 JP. 06/13/1985
62-281523 JP. 12/13/1987
2061575 GB. 05/13/1981

International Class

H03M 005/06

Foreign Application Priority Data

1995-04-14 JP

Abstract

The information to be recorded is divided into 8-bit long data words. Each data word is then converted to 14-bit long code word. The code words are sequentially connected with a one-bit merging bit inserted between the code words to define a code bit sequence. The run-length of 0s in the code bit sequence is limited to be between 2 and 11. The one-bit merging bit normally takes a bit value of 0, but is changed to 1 when any one of the Tmin control or Tmax control is applied so as to accomplish the run-length limitation. The Tmin control is applied when the adjacent bits on both sides of the merging bit are 1s. The Tmax control is applied when trailing P bits of a code word preceding the merging bit and leading Q bits of a code word following the merging bit are all 0s, provided that P+Qࣙ11, and in this case, at least either one of the P bits and Q bits has a bit sequence of (00000), and the bit sequence (00000) is changed to (00100).

Other References

A copy of an International Search Report issued in counterpart PCT application PCT/JP96/00879
Patent Abstracts of Japan, vol. 12, No. 174 (P-612), May 24, 1988
Patent Abstracts of Japan, vol. 9, No. 270 (E-353), Oct. 26, 1985
Patent Abstracts of Japan, vol. 9, No. 258 (E-350), Oct. 16, 1985
A Copy of an International Search Report issued in counterpart PCT application PCT/JP96/00878
A Copy of an International Search Report issued in counterpart PCT application PCT/JP96/00880
English Language Abstract of SHO 63-56610
"Sequence-state Methods for Run-length-limited Coding", by P.A. Franaszek, was published on pp. 376-383 of IBM J. Res. Develop. in Jul., 197