SOI substrate having a high heavy metal gettering effect for semiconductor device
Patent 5773152 Issued on June 30, 1998. Estimated Expiration Date: 
October 13, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 13, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSplit-level CMOS Three-dimensional CMOS inverter Substrate having semiconductor-on-insulator structure with gettering sites and production method thereof Patent #: 5063113 InventorAssigneeApplicationNo. 543068 filed on 10/13/1995US Classes:428/446, Of silicon containing (not as silicon alloy)257/347, Single crystal semiconductor layer on insulating substrate (SOI)257/349, With means (e.g., a buried channel stop layer) to prevent leakage current along the interface of the semiconductor layer and the insulating substrate257/353, Single crystal islands of semiconductor layer containing only one active device257/E21.32, Of silicon on insulator (SOI) (EPO)257/E29.295, Characterized by insulating substrate or support (EPO)428/448, As intermediate layer428/700, Single crystal428/701, O-containing metal compound428/702O-containingExaminersPrimary: Speer, Timothy M.Attorney, Agent or FirmForeign Patent References
International ClassB32B 009/04Foreign Application Priority Data1994-10-13 JPAbstractAn SOI substrate comprises a buried silicon oxide layer formed directly under an active silicon layer, and a layer containing phosphorus therein formed under the buried silicon oxide layer. The layer containing phosphorus therein acts as the getter layer, so that an effective gettering of heavy metals can be obtained in a wide temperature range from a low temperature region to a high temperature region. In addition, since the silicon oxide layer exists between the active layer and the getter layer, the diffusion of the phosphorus into the active layer is effectively prevented, and therefore, the phosphorus scarely diffuses to the active layer, so that the device manufactured is subjected to almost no adverse influence of the diffusion of the phosphorus.Field of SearchField effect device in non-single crystal, or recrystallized, Semiconductor materialIn combination with device formed in single crystal semiconductor material (e.g., stacked FETs) Recrystallized semiconductor material Single crystal semiconductor layer on insulating substrate (SOI) With means (e.g., a buried channel stop layer) to prevent leakage current along the interface of the semiconductor layer and the insulating substrate Single crystal islands of semiconductor layer containing only one active device Of silicon containing (not as silicon alloy) As intermediate layer Single crystal O-containing metal compound O-containing | |
