Ancillary data processing circuit for audio decoding system
Patent 5768281 Issued on June 16, 1998. Estimated Expiration Date: 
April 16, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
April 16, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDecoder for audio signals of compressed and coded audiovisual streams Patent #: 5661728 InventorAssigneeApplicationNo. 633193 filed on 04/16/1996US Classes:370/503, Synchronizing348/384.1, BANDWIDTH REDUCTION SYSTEM348/423.1, Arrangements for multiplexing one video signal, one or more audio signals, and a synchronizing signal370/509Using synchronization information contained in a frameExaminersPrimary: Marcelo, MelvinAttorney, Agent or FirmInternational ClassesH04L 013/00H03K 011/00 Foreign Application Priority Data1995-04-20 JPAbstractThe invention provides an ancillary data processing circuit wherein a bit train of ancillary data having a varying data length is converted into another bit train in units of a byte of a rearwardly packed form to make changing of byte boundaries in following processing unnecessary. The ancillary data processing circuit includes a clock masking circuit including a first 3-bit counter which is reset to zero by a synchronism detection signal and counts a first clock signal, a second 3-bit counter which receives the count value of the first counter as a preset value thereof in response to an ancillary data start signal and counts down a second clock signal, a flip-flop which is initialized in response to the ancillary data start signal, reverses the level thereof in response to an overflow signal of the second counter and outputs a masking signal, and a masking circuit which calculates a combination logic of the masking signal and the second clock signal and outputs the second clock signal or the zero level as a third clock signal in response to the level of the masking signal, and an OR circuit which outputs a result of logical ORing of the first and third clock signals as a read clock signal.Other References
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