Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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US Patent 5765191 - Method for implementing a four-way least recently used (LRU) mechanism in high-performance
US Patent Issued on June 9, 1998
Estimated Patent Expiration Date:
April 29, 2016Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Estimated Patent Expiration Date:
April 29, 2016Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.AbstractA method for implementing a four-way least recently used cache line replacement scheme in a four-way cache memory is disclosed. The cache memory includes multiple cache lines, and each cache line includes four congruence sets. In accordance with the present disclosure, a 5-bit Least Recently Used (LRU) field is associated with each of the cache lines within the cache memory. For a particular cache line, a set number of a least recently used set among the four congruence sets is stored in any two bits of the LRU field associated with that cache line. Next, a set number of the second least recently used set among the four congruence sets is stored in another two bits of the same LRU field associated with the same cache line. Finally, a last bit of the 5-bit LRU field is set to a specific state in response to a determination of which one of the remaining two sets is the second most recently used set. | InventorsApplicationNo. 641060 filed on 04/29/1996US Classes:711/136, Least recently used711/144Cache status data bitField of Search711/133, Entry replacement strategy711/134, Combined replacement modes711/136, Least recently used711/158, Prioritizing711/159, Entry replacement strategy711/160, Least recently used (LRU)711/151Prioritized access regulationExaminersPrimary: Chan, Eddie P.Assistant: Ellis, Kevin L. Attorney, Agent or FirmUS Patent References4607331, Method and apparatus for implementing an algorithm associated with stored informationIssued on: 08/19/1986 Inventor: Goodrich, Jr. , et al.5638531Multiprocessor integrated circuit with video refresh logic employing instruction/data caching and associated timing synchronization Issued on: 06/10/1997 Inventor: Crump, et al. International ClassG06F 012/12 |
