Computer processor having a register file with reduced read and/or write port bandwidth
June 2, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMultiple instruction decoder for minimizing register port requirements Pipelined multi-stage data processor including an operand bypass mechanism Method and apparatus for delaying writing back the results of instructions to a processor Parallel processing method and apparatus Improved method to prefetch load instruction data Processor System for handling load and/or store operations in a superscalar microprocessor Patent #: 5557763 InventorsApplicationNo. 414873 filed on 03/31/1995US Classes:712/218, Commitment control or register bypass712/215Simultaneous issuance of multiple instructionsExaminersPrimary: Treat, William M.Assistant: Winder, Patrice Attorney, Agent or FirmInternational ClassG06F 009/00AbstractA processor is disclosed. The processor relates to a processor having a register file of registers and a dispatch unit capable of issuing up to (i) instructions of a program per cycle to an execution unit having (z) pipelines, wherein some of the instructions specify certain ones of the registers in the register file as source operands and designate certain ones of the registers in the register file as destination registers. The processor also includes a memory for storing the registers of the register file, the memory having (N) access ports configured to access up to (N) registers per cycle, where (N) is less than a maximum number of register values that may need to be accessed during a cycle.Other References
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