Production of substrate for tensilely strained semiconductor
Patent 5759898 Issued on June 2, 1998. Estimated Expiration Date: 
December 19, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 19, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProcess for manufacturing silicon-germanium alloys Patent #: 4857270 Inventors
ApplicationNo. 770065 filed on 12/19/1996US Classes:438/291, Using channel conductivity dopant of opposite type as that of source and drain117/939, Free metal or intermetallic compound or silicon-metal compound based, except arsenic (e.g., alloys, SiGe, InSb) {C30B 29/40, 29/52}148/33.2, With recess, void, dislocation, grain boundaries or channel openings257/E21.125, Defect and dislocati on suppression due to lattice mismatch, e.g., lattice adaptation (EPO)438/292Direct application of electrical currentExaminersPrimary: Kunemund, RobertAttorney, Agent or FirmForeign Patent References
International ClassH01L 021/201AbstractA process and method for producing strained and defect free semiconductor layers. In a preferred embodiment, silicon on insulator may be used as a substrate for the growth of fully relaxed SiGe buffer layers. A new strain relief mechanism operates, whereby the SiGe layer relaxes without the generation of threading dislocations within the SiGe layer. This is achieved by depositing SiGe on an SOI substrate with a superficial silicon thickness. Initially the strain in the SiGe layer becomes equalized with the thin Si layer by creating tensile strain in the Si layer. Then the strain created in the thin Si layer is relaxed by plastic deformation during an anneal. Since dislocations are formed, and glide in the thin Si layer, threading dislocations are not introduced into the upper SiGe material. A strained silicon layer for heterostructures may then be formed on the SiGe material.Other References
Field of SearchFree metal or intermetallic compound or silicon-metal compound based, except arsenic (e.g., alloys, SiGe, InSb) {C30B 29/40, 29/52}With recess, void, dislocation, grain boundaries or channel openings With non-semiconductive coating thereon With contiguous layers of different semiconductive material Having at least three contiguous layers of semiconductive material Including an alloy layer having named impurities Strained layer superlattice Si x Ge 1-x With lattice constant mismatch (e.g., with buffer layer to accommodate mismatch) Using channel conductivity dopant of opposite type as that of source and drain Direct application of electrical current | |
