Gain memory cell with diode
February 19, 2017. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSimultaneous read/write cell Highly scaleable dynamic ram cell with self-signal amplification High density DC stable memory cell Highly scalable dynamic RAM cell with self-signal amplification Dynamic semiconductor memory and manufacturing method thereof Highly scalable dynamic RAM cell with self-signal amplification Semiconductor memory device using diode-capacitor combination Dynamic random access memory cell Semiconductor memory cell for holding data with small power consumption High-speed semiconductor gain memory cell with minimal area occupancy InventorsApplicationNo. 803056 filed on 02/19/1997US Classes:365/149, Capacitors365/230.05Multiple port accessExaminersPrimary: Zarabian, A.Attorney, Agent or FirmForeign Patent References
International ClassG11C 011/24AbstractA gain cell in a memory array having read and write bitlines and wordlines, wherein the gain cell comprises a write transistor, a storage node, a read transistor, and a diode is disclosed. The write transistor allows the value of the write bitline to be stored onto the storage node when activated by the write wordline. The read transistor, which allows the stored value to be read, is coupled to the storage node and to the read bitline via the diode. The diode prevents the conduction of the read transistor in the opposite direction, thus preventing read interference from other cells and reducing bitline capacitance. | |
