Feed-forward bandpass delta-sigma converter with tunable center frequency
October 22, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesHigh order sigma delta oversampled analog-to-digital converter integrated circuit network with minimal power dissipation and chip area requirements Plural-order sigma-delta analog-to-digital converters using both single-bit and multiple-bit quantization Read-out photodiodes using sigma-delta oversampled analog-to-digital converters Third order sigma delta oversampled analog-to-digital converter network with low component sensitivity High-order, plural-bit-quantization sigma-delta modulators using single-bit digital-to-analog conversion feedback Delta sigma analog-to-digital converter with increased dynamic range Multistage bandpass Ɗ Σ modulators and analog-to-digital converters Sigma-delta digital-to-analog converter with reduced noise Sigma-delta analog-to-digital converter with filtration having controlled pole-zero locations, and apparatus therefor Analog-to-digital converters using multistage bandpass delta sigma modulators with arbitrary center frequency InventorsApplicationNo. 734906 filed on 10/22/1996US Classes:341/143, Differential encoder and/or decoder (e.g., delta modulation, differential pulse code modulation)341/155Analog to digital conversionExaminersPrimary: Gaffin, JeffreyAssistant: JeanPierre, Peguy Attorney, Agent or FirmInternational ClassH03M 003/00AbstractDelta sigma modulators for accepting input signals having amplitudes up to -1 dB of full-scale and a center frequency (FS) in the range FS /90, 44F 90!, and which are not prone to internal overflow, require few circuit parameters, and yield a signal transfer function with the inherent property that the modulator magnitude response is close to unity gain in the frequency region of interest include, in one embodiment, a pair of cascaded integrators, a unit delay element coupled to the output of the second integrator, an analog-to-digital (A/D) converter, and a one-bit digital-to-analog (D/A) converter controlled by output signals from the A/D converter. A first differential summing junction coupled to the output of the D/A converter is responsive to delta sigma modulator input signals. A second differential summing junction, coupled to the output of the first differential summing junction, is also coupled to receive a feedback signal from the second integrator. A third differential summing junction, coupled to the output of the unit delay element, also receives feed-forward signals from the second integrator. | |
