Phase measurement apparatus and method
September 10, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDejitterizer method and apparatus Protection channel monitoring system using a check signal comprising two different N-bit code patterns sequentially arranged at random Measurement of timebase jitter for component video Method and apparatus for clock recovery and data retiming for random NRZ data Electroluminescent lamp panel and method of fabricating same Phase locked loop reference slaving circuit Low-power, jitter-compensated phase locked loop and method therefor Device and method for measuring the jitter of a recovered clock signal First order FLL/PLL system with low phase error Mechanism for reducing timing jitter in clock recovery scheme for blind acquisition of full duplex signals InventorAssigneeApplicationNo. 711837 filed on 09/10/1996US Classes:702/75, Frequency327/156, Phase lock loop327/159, With digital element370/516, Adjusting for phase or jitter375/226, Phase error or phase jitter375/371, Phase displacement, slip or jitter correction375/373, Phase locking375/375, With frequency detector and phase detector375/376, Phase locked loop702/69, Signal quality (e.g., timing jitter, distortion, signal-to-noise ratio)702/79, Time-related parameter (e.g., pulse-width, period, delay, etc.)708/313Decimation/interpolationExaminersPrimary: Trammell, James P.Assistant: Nguyen, Hoang Attorney, Agent or FirmInternational ClassesH04L 007/00H04L 025/36 AbstractA phase measurement apparatus and method for measuring electrical signal jitter and wander operates in real time and digitally controls bandwidths over which the measurements are performed. The apparatus includes a digital phase-lock loop (PLL) for generating phase difference signal data having first and second frequency components above and below the loop bandwidth of the phase locked loop. An analog-to-digital converter digitizes the analog phase difference signal from the phase detector. A digital signal processor (DSP) receives the digital data and performs a loop filter function for generating frequency update values to the DDS for phase locking the PLL to an incoming signal. The DSP performs an integration function on the loop filter function output to generate the second frequency components. The first and second frequency components are combined in a summing circuit and filtered in digitally programmable low and high pass filters for establishing measurement bands for measuring the phase difference. A measurement processor measures peak-to-peak minimum and maximum values and generates RMS values of the phase difference signal over a selected time interval and generating an output in unit intervals for jitter and time for wander. The DSP further includes low and high pass filter functions and an accumulator for summing filtered second frequency components to generate wander data. The DSP processes the frequency update values to generate frequency drift data.Other References
Field of SearchPhase displacement, slip or jitter correctionPhase locking With frequency detector and phase detector Phase locked loop Phase error or phase jitter Plural comparators or discriminators Signal or phase comparator Plural active element (e.g., triodes) Tuning compensation Temperature or current responsive means in circuit Phase lock loop With digital element Comparison between plural inputs (e.g., phase angle indication, lead-lag discriminator, etc.) With logic or bistable circuit Synchronizing Adjusting for phase or jitter | |
