Very high-density DRAM cell structure and method for fabricating it
Patent 5753947 Issued on May 19, 1998. Estimated Expiration Date: May 19, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
257/296, Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell)257/302, Vertical transistor257/308, With capacitor electrodes connection portion located centrally thereof (e.g., fin electrodes with central post)257/314, Variable threshold (e.g., floating gate memory device)257/332, Gate electrode self-aligned with groove257/E21.655, Transistor in U- or V-shaped trench in substrate (EPO)257/E27.086, Storage electrode stacked over the transistor257/E27.091Transistor in trench (EPO)
A vertical transistor semiconductor and method of making a vertical transistor is provided. The vertical transistor is particularly suited for use in a DRAM cell. The structure permits a DRAM cell to be fabricated with a comparatively low number of masking layers. Moreover, the vertical nature of the transistor allows a larger number of transistors per surface area compared to conventional techniques. The method and apparatus also utilizes a buried digit line. The digit line may include a portion that is a metal material that in a preferred embodiment is step-shaped sidewall of the digit line. The transistor is particular suited for use with a variety of DRAM capacitors.
Other References
Kim and Kim, "Effects of High-Current Pulses on Polycrystalline Silicon Diode with n-type Region Heavily Doped with Both Boron and Phosphorous," J. Appl. Phys., 53(7):5359-5360, 1982
Neale and Aseltine, "The Application of Amorphous Materials to Computer Memories," IEEE, 20(2):195-205, 1973
Pein and Plummer, "Performance of the 3-D Sidwall Flash EPROM Cell," IEEE, 11-14, 1993
Post and Ashburn, "Investigation of Boron Diffusion in Polysilicon and its Application to the Design of p-n-p Polysilicon Emitter Bipolar Transistors with Shallow Emitter Junctions," IEEE 38(11):2442-2451, 1991
Post et al., "Polysilicon Emitters for Bipolar Transistors: A Review and Re-Evaluation of Theory and Experiment," IEEE, 39(7):1717-1731, 1992
Post and Ashburn, "The Use of an Interface Anneal to Control the Base Current and Emitter Resistance of p-n-p Polysilicon Emitter Bipolar Transistors," IEEE, 13(8):408-410, 1992
Rose et al., "Amorphous Silicon Analogue Memory Devices," J. Non-Crystalline Solids, 115:168-170, 1989
Schaber et al., "Laser Annealing Study of the Grain Size Effect in Polycrystalline Silicon Schottky Diodes," J. Appl. Phys., 53(12):8827-8834, 1982
Yamamoto et al., "The I-V Characteristics of Polycrystalline Silicon Diodes and the Energy Distribution of Traps in Grain Boundaries," Electronics and Communications in Japan, Part 2, 75(7):51-58, 1992
Yeh et al., "Investigation of Thermal Coefficient for Polycrystalline Silicon Thermal Sensor Diode," Jpn. J. Appl. Phys., 31(Part 1, No. 2A):151-155, 1992
Oakley et al., "Pillars -The Way to Two Micron Pitch Multilevel Metallisation," IEEE, 23-29, 198
May 19, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
