Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations
October 3, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system Data processing system with instruction queue having tags indicating outstanding data status Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions Distributed architecture for input/output for a multiprocessor system Cluster architecture for a highly parallel scalar/vector multiprocessor system Method and apparatus for non-sequential resource access Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency Instruction handling sequence control system for simultaneous execution of instructions Dual pipe cache memory with out-of-order issue capability Inventors
ApplicationNo. 538594 filed on 10/03/1995US Classes:712/216, DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION712/217Scoreboarding, reservation station, or aliasingExaminersPrimary: Lim, KrisnaInternational ClassG06F 003/38AbstractA method and apparatus for speculatively dispatching and/or executing LOADs in a computer system includes a memory subsystem of a out-of-order processor that handles LOAD and STORE operations by dispatching them to respective LOAD and STORE buffers in the memory subsystem. When a LOAD is subsequently dispatched for execution, the store buffer is searched for STOREs having unknown addresses. If any STOREs are found which are older than the dispatched LOAD, and which have an unknown address, the LOAD is tagged with an unknown STORE address identification (USAID). When a STORE is dispatched for execution, the LOAD buffer is searched for loads that have been denoted as mis-speculated loads. Mis-speculated loads are prevented from corrupting the architectural state of the machine with invalid data.Other References
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