Self-aligned non-volatile process with differentially grown gate oxide thickness
Patent 5750428 Issued on May 12, 1998. Estimated Expiration Date: 
September 27, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 27, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of making thin oxide portions particularly in electrically erasable and programmable read-only memory cells Method of making flash EEPROM memory Patent #: 5429960 InventorAssigneeApplicationNo. 722799 filed on 09/27/1996US Classes:438/264, Tunneling insulator257/E21.422, With floating gate (EPO)438/766, Implantation of ion (e.g., to form ion amorphousized region prior to selective oxidation, reacting with substrate to form insulative region, etc.)438/770OxidationExaminersPrimary: Niebling, John F.Assistant: Mee, Brendan Attorney, Agent or FirmInternational ClassH01L 021/336AbstractA method of fabricating a novel electrically erasable programmable read only memory (EEPROM) cell for use in semiconductor memories is disclosed herein. Since the degree of ion implantation in the substrate determines the thichness of the silicon dioxide. The proper thickness of the silicon dioxide can be determined by considering the particular dopant to be used and degree of ion implantation, a 50-100 angstroms silicon dioxide is chosen for an arsenic or phosphorus dopant, 1E14-1E15 atoms/cm2, 100 KeV, ion implantation. A 150-350 angstroms silicon dioxide is chosen for an arsenic or phosphorus dopant, 1E11-1E13 atoms/cm2, 100 KeV, ion implantation. The method includes the steps of: forming an isolation layer on a substrate to serve as an isolation; doping ions to form a lightly-doped region in the substrate; patterning a photoresist on the substrate; doping an ions to form a highly-doped region in the substrate; removing the photoresist; oxidizing the substrate to form a gate oxide and a tunnel oxide simultaneously; and forming a first polysilicon layer on the gate oxide and the tunnel oxide. | |
