Method and apparatus for reducing DC component of RLL codes

Patent 5742243 Issued on April 21, 1998. Estimated Expiration Date:

February 14, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

Run-length limited code without DC level
Patent #: 4675650
Issued on: 06/23/1987
Inventor: Coppersmith , et al.

Method and apparatus for converting a run length limited code
Patent #: 4760378
Issued on: 07/26/1988
Inventor: Iketani , et al.

Channel encoder
Patent #: 4779072
Issued on: 10/18/1988
Inventor: van Gestel

Data recording method and data recording apparatus using a digital sum value of a coded signal Patent #: 5451943
Issued on: 09/19/1995
Inventor: Satomura

Inventor

Moriyama, Yoshiaki

Assignee

Pioneer Electric Corporation

Application

No. 599963 filed on 02/14/1996

US Classes:

341/59, To or from run length limited codes341/58To or from minimum d.c. level codes

Examiners

Primary: Fleming, Fritz
Assistant: Kost, Jason L. W.

Attorney, Agent or Firm

Morgan, Lewis & Bockius LLP

International Class

H03M 007/00

Foreign Application Priority Data

1995-02-20 JP

Abstract

Data converting method and apparatus for forming an RLL code which can perform a control to eliminate a DC component without an increase in number of bits. Natural numbers m, n, d, k, and k, satisfy conditions such that m<n and d<k<k1, an input data sequence by binary codes is divided into blocks each consisting of m bits and is sequentially converted to code words every one or a plurality of blocks at a ratio of (m bits:n bits) by a predetermined conversion rule in a manner that after completion of the conversion, the number of bits "0" between neighboring bits "1" is equal to d in minimum and k in maximum. When a value in a predetermined bit pattern in the code word sequence according to the predetermined conversion rule is equal to "1" and the value is changed to "0", a predetermined bit which causes a bit pattern that is not generated by the predetermined conversion rule is used as a control bit, and a value of the control bit is selectively set to "0" or "1", so that a new code word sequence in which the number of bits "10" between the adjacent bits "1" is equal to d in minimum and k1 in maximum and the control of DC component is enabled is formed.