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US Patent 5737334 - Pipeline architecture for an ATM switch backplane bus

US Patent Issued on April 7, 1998
Estimated Patent Expiration Date: Icon_subject September 29, 2015Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
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Abstract

Methods and apparatus providing for a switching hub in which an asynchronous transfer mode (ATM) switch is utilized as a backplane bus to which a plurality of LAN and ATM modules are coupled. Each LAN or ATM module is an autonomous switching module. Thus, for example, an Ethernet LAN module may receive Ethernet packets on one of its ports and transmit the packets out another one of its ports according to well known standards and techniques for bridging such packets, without the need for such packets to be translated into ATM cells and transmitted across the ATM switch backplane bus. In the event a source LAN or ATM module in the switching hub has data to transmit to a destination LAN or ATM module, the destination module is notified prior to transmission of ATM cells across the backplane to the destination module, thus allowing the destination module to schedule reception of the ATM cells off the backplane between its autonomous switching activities, thereby enhancing the utilization of the switching capacity of the autonomous module. Likewise, a source LAN or ATM module is notified two cell slots prior to obtaining ownership of the backplane that, indeed, it will obtain ownership of the backplane bus, so that it may also more fully utilize its switching capacities by performing switching activities during the next two cell slots until such time as it is provided ownership of the backplane data bus and begins transmitting ATM cells to a destination module.

Inventors

Assignee

Application

No. 536133 filed on 09/29/1995

US Classes:

370/395.53, Emulated LAN (LANE/ELAN/VLAN, e.g., Ethernet or token ring legacy LAN over a single ATM network/LAN)370/397, Employing logical addressing for routing (e.g., VP or VC)370/421, Subscribers connected to input or output circuit by a common bus370/428Store and forward

Field of Search

370/389, Switching a message which includes an address header370/392, Processing of address header for routing, per se370/393, Address concatenation370/396Distributed switching

Examiners

Primary: Ton, Dang

Attorney, Agent or Firm

US Patent References

4916692, TDM bus controller
Issued on: 04/10/1990
Inventor: Clarke, et al.
5175727, Communication system network interconnecting a plurality of communication systems
Issued on: 12/29/1992
Inventor: Maher, et al.
5408469, Routing device utilizing an ATM switch as a multi-channel backplane in a communication network
Issued on: 04/18/1995
Inventor: Opher, et al.
5432781, Synchronous node controllers for switching network
Issued on: 07/11/1995
Inventor: Nimon
5481536, Method for restoring a prescribed sequence for unordered cell streams in ATM switching technology
Issued on: 01/02/1996
Inventor: Reisch, et al.
5483527, Terminal adapter for interfacing an ATM network with a STM network
Issued on: 01/09/1996
Inventor: Doshi, et al.
5506969Method and apparatus for bus bandwidth management
Issued on: 04/09/1996
Inventor: Wall, et al.

International Classes

H04L 012/56
397
398
401
407
408
409
421
425
428
451
321
337
347
349

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