FPGA with parallel and serial user interfaces
September 6, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References Re34363 Architectures for serial or parallel loading of writable control store Reconfigurable programmable interconnect architecture Distributed memory architecture for a configurable logic array and method for using distributed memory Interface control logic for embedding a microprocessor in a gate array Programmable gate array with improved interconnect structure, input/output structure and configurable logic block Apparatus and method to improve programming speed of field programmable gate arrays Architecture and interconnect scheme for programmable logic circuits Apparatus for programmable circuit and signal switching Circuit and method of configuring a field programmable gate array InventorsApplicationNo. 465032 filed on 09/06/1995US Classes:716/16, PLA, PLD, FPGA, OR MCM326/38Having details of setting or programming of interconnections or logic functionsExaminersPrimary: Teska, Kevin J.Assistant: Garbowski, Leigh Marie Attorney, Agent or FirmForeign Patent References
International ClassesG06F 017/50H03K 019/173 Foreign Application Priority Data1995-05-02 GBAbstractA configuration structure for a field programmable gate array (FPGA) allows a user to reconfigure or partly reconfigure the FPGA from within the FPGA, allows an addressable configuration memory to be addressed in parallel through a set of address and data or through a serial interface. Signals such as chip-enable and other control signals can be modified by user logic so that data loaded through a serial interface pin is entered into an addressed portion of configuration memory. The configuration memory programs not only the internal circuitry accessed by the user but also a programmable switch for directing signals between external pins, configuration memory control lines, and a serial data interface. Providing both parallel and serial interfaces allows a programmable switch which is initially configured to connect its related pad or pads to configuration control lines such as a chip enable line or a serial data input line to later be configured to connect an internally generated signal or signals to the line or lines and thus override any external signal which would have been connected to that line or lines.Other References
Field of SearchHaving details of setting or programming of interconnections or logic functionsArray (e.g., PLA, PAL, PLD, etc.) Significant integrated structure, layout, or layout interconnections Significant integrated structure, layout, or layout interconnections SIGNIFICANT INTEGRATED STRUCTURE, LAYOUT, OR LAYOUT INTERCONNECTIONS | |
