Phase locked loop using a counter and a microcontroller to produce VCXO control signals
Patent 5726607 Issued on March 10, 1998. Estimated Expiration Date: 
March 10, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
March 10, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesRedundant clock signal generating circuitry Control system for adjusting a physical quantity Phase locked loop wherein phase comparing and filtering are performed by microprocessor Patent #: 4864253 InventorsAssigneeApplicationNo. 192071 filed on 02/04/1994US Classes:331/2, Plural oscillators controlled331/14, With intermittent comparison controls331/17, Particular error voltage control (e.g., intergrating network)331/25Signal or phase comparatorExaminersPrimary: Grimm, Siegfried H.Attorney, Agent or FirmInternational ClassH03L 007/07AbstractA digitally controlled phase locked loop generates a derived clock signal that is frequency locked to a reference clock signal. The apparatus is comprised of a microcontroller, counter, digital to analog converter (DAC) and a voltage controlled crystal oscillator (VCXO) connected in a feedback loop arrangement. A frequency output derived from the VCXO periodically samples an incoming reference signal. The sampled count value is compared to an ideal count value associated with the same sampling time period. A microcontroller and software-based algorithm perform the phase comparison and loop filter operations of the phase locked loop (PLL). | |
