Abstract

A virtual high density architecture having shared memory cells for a programmable integrated circuit (IC) is provided. The architecture includes logic modules, a configuration memory unit (CMU), and a global interconnect memory (GIMU) unit. A logic cycle is divided into a number of time intervals. For each time interval, the CMU outputs information to configure the logic modules and the interconnect structure to realize an individual circuit stage of a circuit. Input and output data pertinent to this individual stage are retrieved from and stored in the GIMU based on addressing information generated from the CMU for each time interval. The CMU continuously reprograms the logic modules and interconnect structure for each time interval to realize different stages of the circuit while information used between stages is stored in the GIMU. The architecture reuses the IC's complement of logic and other functional elements continuously during a logic cycle to implement the circuit as a series of circuit stages over time using a relatively limited number of logic and other functional elements to implement each stage. The GIMU is coupled to address and data buses and the data bus is coupled to each logic module. The GIMU contains individually addressable memory cells that are shared between logic modules across different time intervals providing an extremely flexible signal path between logic modules. The GIMU has a separate read and write port for each logic module.

Other References

• N.B. Bhat,, et al., "Performance Oriented Fully Routable Dynamic Architecture for a Field Programmable Logic Device", Electronics Research Laboratory of U.C. Berkeley, Jun. 1, 199