Flash EEPROM system

Patent 5719808 Issued on February 17, 1998. Estimated Expiration Date:

March 21, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

3895360

3898632

3906455

3914750

Arrangement for reducing the access time in a storage system
Patent #: 4005389
Issued on: 01/25/1977
Inventor: Penzel

Block oriented random access memory
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Issued on: 08/23/1977
Inventor: Berg

Block oriented random access bubble memory
Patent #: 4058799
Issued on: 11/15/1977
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Patent #: 4090258
Issued on: 05/16/1978
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Patent #: 4099069
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Inventors

Assignee

SanDisk Corporation

Application

No. 407916 filed on 03/21/1995

US Classes:

365/185.33, Flash365/185.22, Verify signal365/185.29Erase

Examiners

Primary: Popek, Joseph A.

Attorney, Agent or Firm

Majestic, Parsons, Siebert & Hsue

Foreign Patent References

0283238 EP. 09/26/1988
52-8738 JP. 01/26/1977
58-86777 JP. 05/26/1983
58-215794 JP. 12/26/1983
58-215795 JP. 12/26/1983
945695 JP. 03/26/1984
59-162695 JP. 09/26/1984
59-186015 JP. 10/26/1984
62-188099 JP. 08/26/1987
62-283496 JP. 12/26/1987
62-283497 JP. 12/26/1987
63-18596 JP. 01/26/1988
63-106989 JP. 05/26/1988
63-183700 JP. 07/26/1988
63-225999 JP. 09/26/1988

International Class

G11C 011/34

Abstract

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Other References

J.E. Brewer et al., "Block-Oriented Random Access MNOS Memory," National Computer Conference and Exposition, Chicago, May 6-10, 1974, AFIPS Conference Proceedings, vol. 43
J.E. Brewer et al., "Low Cost MNOS BORAM," Proceedings of IEEE National Aerospace Electronics Conference, NAECON '77, May 17-19, 1977
J.R. Cricchi et al., "Nonvolitile Block-Oriented RAM," IEEE International Solid-State Circuits Conference, Feb. 13-15, 1974, Digest of Technical Papers
Raul-Adrian Cernea et al., "A 1Mb Flash EEPROM," 1989 IEEE International Solid-State Circuits Conference
Kenneth L. Short, "Microprocessors and Programmed Logic," second edition. Ch. 13.2.2 Electrically Erasable Programmable Read Only Memory, EEPROM Prentice Hall International, 1987
Michael D. Fitzpatrick et al., "MNOS/SOS Memory Using High-Voltage Depletion-Mode CMOS Logic"
J.R. Cricchi et al., "The Drain-Source Protected MNOS Memory Device and Memory Endurance," IEDM Technical Digest, 1973
Virgil Kynett et al., "An In-System Reprogrammable 32K×8 CMOS Flash Memory," IEEE J. Solid-State Circuits, vol. 23, No. 5, Oct., 1988
Denny Cormier, "Erasable/Programmable Solid-State Memories," EDN, pp. 145-154, Nov. 14, 1985
Colin S. Bill, et al.; A Temperature- and Process- Tolerant 64K EEPROM, 1985, pp. 979-985
Intel Corporation, 27F256 256K (32K×8) CMOS Flash Memory, Data Sheet, May 1988, pp. 1-21
SEEQ Technology Incorp., 48F512 512K Flash EEPROM--Preliminary Data Sheet, Oct. 1988, pp. 2-1--2-24
Wilson, "1-Mbit flash memories seek their role in system design," Computer Design, (Mar. 1, 1989) pp. 30 and 3