System for coordinating coherency of cache memories of multiple host computers of a distributed information system
Patent 5717897 Issued on February 10, 1998. Estimated Expiration Date: 
September 9, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 9, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesData processing system having a data coherence solution Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system Distributed arbitration method and apparatus for a computer bus using arbitration groups Apparatus and method for achieving reduced overhead mutual exclusion and maintaining coherency in a multiprocessor system utilizing execution history and thread monitoring Patent #: 5442758 InventorApplicationNo. 709595 filed on 09/09/1996US Classes:711/141, Coherency707/8, Concurrency (e.g., lock management in shared database)710/111Rotational prioritizing (i.e., round robin)ExaminersPrimary: Swann, Tod R.Assistant: Langjahr, David Attorney, Agent or FirmInternational ClassG06F 015/80AbstractApparatus and method for coordinating cache coherency between host cache memories in a distributed information system in a system which comprises at least one main storage memory coupled to a plurality of host computers through controllers. Each host computer includes a host cache controller which maintains the state of the data stored in its associated memory and maintains communicating with a main memory controller for participating in the control of coordinated reading and writing of data between the host cache memories and the main storage memory. The system maintains cache coherency by the exchange of commands between the main memory controller and the hosts cache controllers each of which define the state of the blocks of data stored in the host cache memories.Other References
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