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US Patent 5714766 - Nano-structure memory device

US Patent Issued on February 3, 1998
Estimated Patent Expiration Date: Icon_subject September 29, 2015Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
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Abstract

A memory device and memory incorporating a plurality of the memory devices is described wherein each memory device has spaced apart source and drain regions, a channel, a barrier insulating layer, a nanocrystal or a plurality of nanocrystals, a control barrier layer, and a gate electrode. The nanocrystal which may be a quantum dot, stores one electron or hole or a discrete number of electrons or holes at room temperature to provide threshold voltage shifts in excess of the thermal voltage for each change in an electron or a hole stored. The invention utilizes Coulomb blockade in electrostatically coupling one or more stored electrons or holes to a channel while avoiding in-path Coulomb-blockade controlled conduction for sensing the stored charge.

Other References

  • Nicollian et al., "Electrical properties of a silicon quantum dot diode", J. Appl. Phys. 74, 4020 (1993)
  • K. Yano et al., "A room-temperature single-electron memory device using a fine-grain polycrystalline silicon", Dig. of Int'l Electron Dev. Mtg, Dec. 1993, Washington D. C., p. 541
  • K. Bock et al., "Proposal for the concept of ultradense integrated memories based on Coulomb blockade at room temperature", Electron Letters, 29, 2228 (1993)
  • Likharev et al., "Single Electronics" Scientific American, Jun. 1992, pp. 80-85
  • Wind et al., "Computer take a quantum leap", BYTE, vol. 17, No. 2, Feb. 1992, McGraw Hill, Inc., p. 140
  • Matsuoka et al., "Coulomb Blockade in the inversion layer of a Si metal-oxide-semiconductor field-effect transistor with a dual-gate structure", Appl. Phys. Lett. 64, 586, Jan. 199

Inventors

Application

No. 536510 filed on 09/29/1995

US Classes:

257/17, With particular barrier dimension257/20, Field effect device257/22, With specified semiconductor materials257/24, Field effect device257/E21.422, With floating gate (EPO)257/E29.301, Programmable by two single electrons (EPO)257/E29.308, Programmable with more than two possible different levels (EPO)365/174, Semiconductive365/182Insulated gate devices

Field of Search

257/20, Field effect device257/17, With particular barrier dimension257/22, With specified semiconductor materials257/24, Field effect device365/174, Semiconductive365/182Insulated gate devices

Examiners

Primary: Mintel, William

Attorney, Agent or Firm

US Patent References

4998236, Apparatus for high density holographic optical data storage
Issued on: 03/05/1991
Inventor: Henshaw
5055890, Nonvolatile semiconductor memory having three dimension charge confinement
Issued on: 10/08/1991
Inventor: Dawson, et al.
5233205, Quantum wave circuit
Issued on: 08/03/1993
Inventor: Usagawa, et al.
5347140, Resonant electron transfer device
Issued on: 09/13/1994
Inventor: Hirai, et al.
5440148Quantum operational device
Issued on: 08/08/1995
Inventor: Nomoto

Foreign Patent References

  • 05-129589 JP. 05/17/1993
  • 07-249781 JP. 09/17/1995
  • 07-297381 JP. 11/17/1995
  • 07-302886 JP. 11/17/1995

International Classes

H01L 029/06
H01L 031/032.8
H01L 031/033.6

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