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Process for dividing instructions of a computer program into instruction groups for parallel processing

Patent 5712996 Issued on January 27, 1998. Estimated Expiration Date: Icon_subject September 14, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Parallel processor system for processing natural concurrencies and method therefor
Patent #: 5021945
Issued on: 06/04/1991
Inventor: Morrison, et al.

System for compiling iterated loops based on the possibility of parallel execution
Patent #: 5317743
Issued on: 05/31/1994
Inventor: Imai, et al.

Compiler with delayed conditional branching Patent #: 5450585
Issued on: 09/12/1995
Inventor: Johnson

Inventor

Assignee

Application

No. 513976 filed on 09/14/1995

US Classes:

712/216, DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION717/149, For a parallel or multiprocessor system717/151Optimization

Examiners

Primary: Lall, Parshotam S.
Assistant: Patel, Gautam R.

Attorney, Agent or Firm

Foreign Patent References

  • 0 501 653 EP. 09/13/1992
  • WO 91/20031 WO. 12/13/1991

International Class

G06F 009/40

Foreign Application Priority Data

1993-03-15 DE

Abstract

In order to be able to execute rapid processing of a program on super-scalar microprocessors, the individual instructions of this program must be divided into instruction groups, which can be processed by processing units of the microprocessor, in such a way that the instructions can be processed in parallel. In this case, it is necessary to take account of data-flow dependences and control-flow dependences as well as pipeline conflicts. For this purpose, the first step is to select the instructions whose precursor instructions have already been processed and to investigate these instructions as to whether before their execution a minimum number of delay cycles is necessary, and the instructions are stored with a minimum number in a list. From these instructions, one is selected using a heuristic selection process, and this one is classified into an instruction group in which the instruction can be processed in the earliest possible execution cycle.

Other References

  • "Efficient Instruction Scheduling for a Pipelined Architecture" by P.B. Gibbons and S.S. Muchnick, Sigplan Notices, vol. 21, No. 7, Jul. 1986, pp. 11-16
  • "Instruction Scheduling for the IBM RISC System/6000 Processor", by H.S. Warren, Jr., IBM Journal of Research and Development, vol. 34, No. 1, Jan. 1990, pp. 85-92
  • "Performance Evaluation for Various Configuration of Superscalar Processors", by A. Inoue and K. Takeda, Computer Architecture News, vol. 21, No. 1, Mar. 1993, pp. 4-11
  • "An Efficient Algorithm for Exploiting Multiple Arithmetic Units", by R.M. Tomasulo, IBM Journal of Research and Development, Jan. 1967, pp. 25-33
  • "A Brief Survey of Papers on Scheduling for Pipelined Processors", by S.M. Krishnamurthy, Sigplan Notices, vol. 25, No. 7, Jul. 1990, pp. 97-100
  • "Trace Scheduling: A Technique for Global Microcode Compaction", by J.A. Fisher, IEEE Transactions on Computers, vol. 30, No. 7, Jul. 1981, pp. 478-49
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