Conversion characteristic test circuit for analog/digital converter and method thereof
Patent 5712633 Issued on January 27, 1998. Estimated Expiration Date: 
January 3, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
January 3, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesBuilt-in self test for analog to digital converters Method and apparatus for testing an analog to digital converter Test device of analog/digital converter Analogue-to-digital converters, digital-to-analogue converters, and digital modulators Digital linearization calibration for analog to digital converter Analog-to-digital converter with digital linearity correction Patent #: 5594612 InventorAssigneeApplicationNo. 582265 filed on 01/03/1996US Classes:341/120, CONVERTER CALIBRATION OR TESTING324/73.1, PLURAL, AUTOMATICALLY SEQUENTIAL TESTS341/155Analog to digital conversionExaminersPrimary: Gaffin, JeffreyAssistant: Kost, Jason L. W. Attorney, Agent or FirmInternational ClassH03M 001/12Foreign Application Priority Data1995-10-13 KRAbstractA conversion characteristic test circuit and method for an A/D converter uses a DNL error, an INL error, and a dynamic conversion characteristic to analyze digital data output from an A/D converter for judging an operation state of the A/D converter. The conversion characteristic test circuit includes a data detecting unit that detects a digital code randomly output from the A/D converter. A test signal generating unit generates a sequential test signal in accordance with a test clock signal. A DNL error data detecting unit receives a data output by the data detecting unit in accordance with the sequential test signal and subtracts the data from an code-by ideal data to compute DNL error data. An INL error data detecting unit computes INL error data based on the DNL error data and the test clock signal. A judging unit receives the outputs of the DNL error data detecting unit and the INL error data detecting unit and detects a DNL error and an INL error to judge an operation state of the A/D converter. | |
