High density two port SRAM cell for low voltage CMOS applications
May 12, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesRegister providing simultaneous reading and writing to multiple ports Writing speed in multi-port static rams Static random access memory device with pull-down control circuit Hardware enhancements for improved performance of memory emulation method Multiport memory device Dual-port memory with read and read/write ports Semiconductor memory device Dual-port static random access memory cell Memory device with multiple read ports Memory cell for use in a multi-port RAM InventorsApplicationNo. 440285 filed on 05/12/1995US Classes:365/230.05, Multiple port access365/154, Flip-flop (electrical)365/189.05Having particular data buffer or latchExaminersPrimary: Nelms, David C.Assistant: Le, Vu A. Attorney, Agent or FirmInternational ClassG11C 011/00AbstractA two-port memory cell design which permits simultaneous reading and writing of cells which are on the same wordline but on different Bit Select lines without increase in Read Access Time, and while maintaining memory functionality at low voltages. The memory cell uses a standard 6 transistor design to provide a differential read for fast access plus another three transistors are added to each cell to provide a means of differentially writing the cell and de-gating the write if the bit-select is not active. This cell design has applicability to multi-port memories as well. | |
