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US Patent 5710450 - Transistor with ultra shallow tip and method of fabrication
US Patent Issued on January 20, 1998
Estimated Patent Expiration Date:
January 20, 2015Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Estimated Patent Expiration Date:
January 20, 2015Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.AbstractA novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip region comprising an ultra shallow region which extends beneath the gate electrode and a raised region.Other References
| InventorsApplicationNo. 363749 filed on 12/23/1994US Classes:257/344, With lightly doped portion of drain region adjacent channel (e.g., LDD structure)257/19, Si x Ge 1-x257/65, Non-single crystal, or recrystallized, material containing non-dopant additive, or alloy of semiconductor materials (e.g., Ge x Si 1- x, polycrystalline silicon with dangling bond modifier)257/336, With lightly doped portion of drain region adjacent channel (e.g., LDD structure)257/377, With polysilicon interconnections to source or drain regions (e.g., polysilicon laminated with silicide)257/382, With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide)257/385, Multiple polysilicon layers257/408, Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device)257/742, With a semiconductor conductivity substitution type dopant (e.g., germanium in the case of a gallium arsenide semiconductor) in a contact metal)257/755, Polysilicon laminated with silicide257/773, Of specified configuration257/E21.148, From or through or into an applied layer, e.g., photoresist, nitride (EPO)257/E21.151, Applied layer being silicon or silicide or SIPOS, e.g., polysilicon, porous silicon (EPO)257/E21.201, Conductor layer next to insulator is Si or Ge or C and their non-Si alloys (EPO)257/E21.43, Recessing gate by adding semiconductor material at source (S) or drain (D) location, e.g., transist or with elevated single crystal S and D (EPO)257/E21.431, With source and drain recessed by etching or recessed and refi lled (EPO)257/E21.435, Lateral single gate single channel silicon transistor with both lightly doped source and drain extensions and source and drain self-aligned to sides of gate, e.g., LDD MOSFET, DDD MOSFET (EPO)257/E21.438, Using self-aligned silicidation, i.e., salicide (EPO)257/E21.634, With particular manufacturing method of source or drain, e.g., specific S or D implants or silicided S or D structures or raised S or D structures (EPO)257/E21.64, With particular manufacturing method of gate sidewall spacers, e.g., double spacers, particular spacer material or shape (EPO)257/E29.04, Of field-effect transistors with insulated gate (EPO)257/E29.122, Characterized by relative position of source or drain electrode and gate electrode (EPO)257/E29.143, Ohmic electrodes (EPO)257/E29.155, Multiple silicon layers257/E29.156, Including silicide layer contacting silicon layer (EPO)257/E29.267, With nonplanar structure (e.g., gate or source or drain being nonplanar) (EPO)438/300, Having elevated source or drain (e.g., epitaxially formed source or drain, etc.)438/303, Utilizing gate sidewall structure438/305, Plural doping steps438/586Combined with formation of ohmic contact to semiconductor regionField of Search257/19, Si x Ge 1-x257/65, Non-single crystal, or recrystallized, material containing non-dopant additive, or alloy of semiconductor materials (e.g., Ge x Si 1- x, polycrystalline silicon with dangling bond modifier)257/382, With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide)257/742, With a semiconductor conductivity substitution type dopant (e.g., germanium in the case of a gallium arsenide semiconductor) in a contact metal)257/755, Polysilicon laminated with silicide257/377, With polysilicon interconnections to source or drain regions (e.g., polysilicon laminated with silicide)257/385, Multiple polysilicon layers257/773, Of specified configuration257/336, With lightly doped portion of drain region adjacent channel (e.g., LDD structure)257/344, With lightly doped portion of drain region adjacent channel (e.g., LDD structure)257/408Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device)ExaminersPrimary: Wojciechowicz, EdwardAttorney, Agent or FirmUS Patent References4998150, Raised source/drain transistorIssued on: 03/05/1991 Inventor: Rodder, et al.5079180, Method of fabricating a raised source/drain transistor Issued on: 01/07/1992 Inventor: Rodder, et al.5168072, Method of fabricating an high-performance insulated-gate field-effect transistor Issued on: 12/01/1992 Inventor: Moslehi5285088, High electron mobility transistor Issued on: 02/08/1994 Inventor: Sato, et al.5336903, Selective deposition of doped silicon-germanium alloy on semiconductor substrate, and resulting structures Issued on: 08/09/1994 Inventor: Ozturk, et al.5397909, High-performance insulated-gate field-effect transistor Issued on: 03/14/1995 Inventor: Moslehi5405795Method of forming a SOI transistor having a self-aligned body contact Issued on: 04/11/1995 Inventor: Beyer, et al. International ClassesH01L 029/06H01L 021/265 |
