Semiconductor memory device for simple cache system
Method and apparatus for buffering a user application from the timing requirements of a DRAM Patent #: 5615355
ApplicationNo. 672373 filed on 05/29/1996
US Classes:345/535, Memory arbitration345/558, First in first out (i.e., FIFO)345/572, Address generator711/100, STORAGE ACCESSING AND CONTROL711/105Dynamic random access memory
ExaminersPrimary: Tung, Kee M.
Attorney, Agent or Firm
International ClassG06F 013/16
Foreign Application Priority Data1995-05-31 JP
AbstractIn order to write data flowing in continuously into an image memory consisting of a single port RAM without lack and to read data out of the image memory continuously without lack in parallel, a memory access processor of the invention comprises;a write buffer for storing temporarily data flowing in continuously and outputting write requests while data are stored therein,a read buffer for storing temporarily data output from the image memory to be read out therefrom continuously, andan arbiter section for arbitrating concurrence between write requests and read requests for the image memory, writing data stored in the write buffer at a speed higher than a speed of data writing into the write buffer when write actions are performed according to the write requests, and reading data out of the image memory to be stored in the read buffer at a speed higher than a speed of data readout from the read buffer when read actions are performed according to the read requests.