Dual damascene with a sacrificial via fill
June 7, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProcess for forming a self-aligned contact structure Method of making integrated circuits having a planarized dielectric Laser ablation damascene process Process for forming a contact structure Process for fabrication of a semiconductor structure and contact stud Refractory metal capped low resistivity metal conductor lines and vias Method of forming a semiconductor structure having an air region Method of forming metal connections Chip interconnection having a breathable etch stop layer Method for fabricating connection device with reduced area of highly integrated semiconductor device InventorsAssigneeApplicationNo. 486777 filed on 06/07/1995US Classes:438/618, Contacting multiple semiconductive regions (i.e., interconnects)257/E21.585, Filling of holes, grooves, vias or trenches with conductive material (EPO)438/669, And patterning of conductive layer438/672, Plug formation (i.e., in viahole)438/702Plural coating stepsExaminersPrimary: Gorgos, KathrynAssistant: Carroll, Chrisman D. Attorney, Agent or FirmInternational ClassH01L 021/44AbstractA dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a sacrificial via fill. A first layer of insulating material is formed with via openings. The openings are filled with a sacrificial removable material. A second layer of insulating material is deposed on the first layer. In one embodiment, the etch selectivity to the etchant of the second layer is essentially the same as the sacrificial via fill and, preferably, is substantially higher than second layer. Using a conductive line pattern aligned with the via openings, conductive line openings are etched in the second insulating layer and, during etching, the sacrificial fill is removed from the via openings. In a second embodiment, the sacrificial material is not etchable by the etchant for forming the conductive line openings and, after formation of the conductive line openings, the sacrificial material is removed with an etchant to which the first insulating layer is resistive or less selective. A conductive material now is deposited in the conductive line and via openings. | |
