Non-volatile semiconductor memory device erasing operation
Nonvolatile semiconductor memory device and data erasing method thereof
Non-volatile semiconductor memory device in which data can be erased on a block basis and method of erasing data on a block basis in non-volatile semiconductor memory device
Nonvolatile semiconductor memory device
Semiconductor memory device having an energy gap for high speed operation
Method for optimum erasing of EEPROM
Floating gate or flash EPROM transistor array having contactless source and drain diffusions
Self-recovering erase scheme to enhance flash memory endurance
Single transistor flash EPROM cell and method of operation
Programming method for the selective healing of over-erased cells on a flash erasable programmable read-only memory device
ApplicationNo. 718525 filed on 10/07/1996
US Classes:365/185.18, Particular biasing365/185.22, Verify signal365/185.24, Threshold setting (e.g., conditioning)365/185.33Flash
ExaminersPrimary: Nguyen, Tan T.
Attorney, Agent or Firm
International ClassG11C 016/00
AbstractSubstantial reduction in peak current encountered during an erase process for a flash memory device is achieved by selection of source voltage potential during the erase according to the expected band-to-band tunneling current encountered during the process. During the beginning of the process, a lower source voltage potential is selected, which is high enough to cause significant erasing while suppressing band-to-band tunneling current in a portion of the array, and during a second part of the erasing process, a higher source potential is utilized, which ensures successful erasing of the array, without exceeding the peak current requirements of the power supply used with the device. The first and second parts of the erase sequence will induce band-to-band tunneling current in addition to Fowler-Nordheim tunneling current. The band-to-band tunneling current is characterized by a turn on threshold source potential which is inversely related to the threshold of the cell receiving the voltage sequence. The source voltage used in the first part of the erase sequence is set at level that is near or above the turn on threshold source potential for higher threshold cells that are in the high threshold state, but less than the turn on threshold source potential for lower threshold cells in the high threshold state. The source potential in the second part is set at level which is near or above the turn on threshold source potential for lower threshold cells in the high threshold state.