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US Patent 5696956 - Dynamically programmable reduced instruction set computer with programmable processor loading on program number field and program number register contents
US Patent Issued on December 9, 1997
Estimated Patent Expiration Date:
November 8, 2015Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Estimated Patent Expiration Date:
November 8, 2015Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.AbstractA new class of general purpose computers called Programmable Reduced Instruction Set Computers (PRISC) use RISC techniques a basis for operation. In addition to the conventional RISC instructions, PRISC computers provide hardware programmable resources which can be configured optimally for a given user application. A given user application is compiled using a PRISC compiler which recognizes and evaluates complex instructions into a Boolean expression which is assigned an identifier and stored in conventional memory. The recognition of instructions which may be programmed in hardware is achieved through a combination of bit width analysis and instruction optimization. During execution of the user application on the PRISC computer, the stored expressions are loaded as needed into a programmable functional unit. Once loaded, the expressions are executed during a single instruction cycle.Other References
| InventorsAssigneeApplicationNo. 554643 filed on 11/08/1995US Classes:712/23, Superscalar700/2, Plural processors712/43, Mode switching712/200ARCHITECTURE BASED INSTRUCTION PROCESSINGExaminersPrimary: Kim, Kenneth S.Attorney, Agent or FirmUS Patent References5361373, Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method thereforIssued on: 11/01/1994 Inventor: Gilson5404472, Parallel processing apparatus and method capable of switching parallel and successive processing modes Issued on: 04/04/1995 Inventor: Kurosawa, et al.5448746, System for comounding instructions in a byte stream prior to fetching and identifying the instructions for execution Issued on: 09/05/1995 Inventor: Eickemeyer, et al.5452456, Apparatus for executing a plurality of program segments having different object code types in a single program or processor environment Issued on: 09/19/1995 Inventor: Mourey, et al.5542059Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order Issued on: 07/30/1996 Inventor: Blomgren International ClassG06F 009/30 |
