Dynamically programmable reduced instruction set computer with programmable processor loading on program number field and program number register contents

Patent 5696956 Issued on December 9, 1997. Estimated Expiration Date:

November 8, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

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Inventors

Assignee

Digital Equipment Corporation

Application

No. 554643 filed on 11/08/1995

US Classes:

712/23, Superscalar700/2, Plural processors712/43, Mode switching712/200ARCHITECTURE BASED INSTRUCTION PROCESSING

Examiners

Primary: Kim, Kenneth S.

Attorney, Agent or Firm

Dagg; David A., Ross; Gary E., Fisher; Arthur W.

International Class

G06F 009/30

Abstract

A new class of general purpose computers called Programmable Reduced Instruction Set Computers (PRISC) use RISC techniques a basis for operation. In addition to the conventional RISC instructions, PRISC computers provide hardware programmable resources which can be configured optimally for a given user application. A given user application is compiled using a PRISC compiler which recognizes and evaluates complex instructions into a Boolean expression which is assigned an identifier and stored in conventional memory. The recognition of instructions which may be programmed in hardware is achieved through a combination of bit width analysis and instruction optimization. During execution of the user application on the PRISC computer, the stored expressions are loaded as needed into a programmable functional unit. Once loaded, the expressions are executed during a single instruction cycle.