U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Semiconductor device and method of manufacturing the same

Patent 5696008 Issued on December 9, 1997. Estimated Expiration Date: Icon_subject June 21, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Process for forming complementary integrated circuit devices
Patent #: 4435895
Issued on: 03/13/1984
Inventor: Parrillo ,   et al.

Method of producing insulated gate MOSFET employing polysilicon mask
Patent #: 4914047
Issued on: 04/03/1990
Inventor: Seki

Method of fabricating a vertical FET device with low gate to drain overlap capacitance
Patent #: 5073519
Issued on: 12/17/1991
Inventor: Rodder

Semiconductor vertical MOSFET inverter circuit
Patent #: 5311050
Issued on: 05/10/1994
Inventor: Nitayama, et al.

Method of making vertically stacked bipolar semiconductor structure
Patent #: 5426059
Issued on: 06/20/1995
Inventor: Queyssac

Method of making power VFET device Patent #: 5468661
Issued on: 11/21/1995
Inventor: Yuan, et al.

Inventors

Assignee

Application

No. 668180 filed on 06/21/1996

US Classes:

438/212, Vertical channel257/E21.638, Gate conductors with different shapes, lengths or dimensions (EPO)257/E21.643, With particular manufacturing method of vertical transistor structures, i.e., with channel vertical to substrate surface (EPO)257/E27.064, Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS (EPO)438/268Vertical channel

Examiners

Primary: Niebling, John F.
Assistant: Lebentritt, Michael S.

Attorney, Agent or Firm

International Classes

H01L 021/265
H01L 021/70

Foreign Application Priority Data

1994-08-25 JP

Abstract

On a semiconductor substrate made of p-type silicon, there are formed, in a successively layered fashion, a first p-type silicon semiconductor layer, laterally paired first n-type silicon semiconductor layers, laterally paired second p-type silicon semiconductor layers, and laterally paired n-type silicon semiconductor layers, by an epitaxial growth method. On the second n-type silicon semiconductor layer on the right side, there are successively formed a third p-type silicon semiconductor layer, a third n-type silicon semiconductor layer and a fourth p-type silicon semiconductor layer. The left first n-type silicon semiconductor layer, left second p-type silicon semiconductor layer and left second n-type silicon semiconductor layer form a first insular multilayered portion forming an n-channel MOSFET. The third p-type silicon semiconductor layer, third n-type silicon semiconductor layer and fourth p-type silicon semiconductor layer form a second insular portion forming a p-channel MOSFET. A first gate electrode is formed on a side surface of the left second p-type silicon semiconductor layer with a gate insulating film therebetween, and a second gate electrode is formed on a side surface of the right third n-type silicon semiconductor layer with a gate insulating film therebetween.

PatentsPlus Images
Enhanced PDF formats
loading...
PatentsPlus: add to cart
PatentsPlus: add to cartSearch-enhanced full patent PDF image
$9.95more info
PatentsPlus: add to cart
PatentsPlus: add to cartIntelligent turbocharged patent PDFs with marked up images
$18.95more info
 
Sign InRegister
Username  
Password   
forgot password?