Patent ReferencesProcess for forming complementary integrated circuit devices Method of producing insulated gate MOSFET employing polysilicon mask Method of fabricating a vertical FET device with low gate to drain overlap capacitance Semiconductor vertical MOSFET inverter circuit Method of making vertically stacked bipolar semiconductor structure Method of making power VFET device Patent #: 5468661 InventorsAssigneeApplicationNo. 668180 filed on 06/21/1996US Classes:438/212, Vertical channel257/E21.638, Gate conductors with different shapes, lengths or dimensions (EPO)257/E21.643, With particular manufacturing method of vertical transistor structures, i.e., with channel vertical to substrate surface (EPO)257/E27.064, Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS (EPO)438/268Vertical channelExaminersPrimary: Niebling, John F.Assistant: Lebentritt, Michael S. Attorney, Agent or FirmInternational ClassesH01L 021/265H01L 021/70 Foreign Application Priority Data1994-08-25 JPAbstractOn a semiconductor substrate made of p-type silicon, there are formed, in a successively layered fashion, a first p-type silicon semiconductor layer, laterally paired first n-type silicon semiconductor layers, laterally paired second p-type silicon semiconductor layers, and laterally paired n-type silicon semiconductor layers, by an epitaxial growth method. On the second n-type silicon semiconductor layer on the right side, there are successively formed a third p-type silicon semiconductor layer, a third n-type silicon semiconductor layer and a fourth p-type silicon semiconductor layer. The left first n-type silicon semiconductor layer, left second p-type silicon semiconductor layer and left second n-type silicon semiconductor layer form a first insular multilayered portion forming an n-channel MOSFET. The third p-type silicon semiconductor layer, third n-type silicon semiconductor layer and fourth p-type silicon semiconductor layer form a second insular portion forming a p-channel MOSFET. A first gate electrode is formed on a side surface of the left second p-type silicon semiconductor layer with a gate insulating film therebetween, and a second gate electrode is formed on a side surface of the right third n-type silicon semiconductor layer with a gate insulating film therebetween.Field of SearchVertical channel or double diffused insulated gate field effect device provided with means to protect against excess voltage (e.g., gate protection diode)Gate controls vertical charge flow portion of channel (e.g., VMOS device) With means to prevent latchup or parasitic conduction channels | |