Technique for producing small islands of silicon on insulator
September 4, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProcess for producing NPN type lateral transistor with minimal substrate operation interference Method of producing integrated silicon structures on isolated islets of the substrate PNP-type lateral transistor with minimal substrate operation interference and method for producing same Formation and planarization of silicon-on-insulator structures Method of forming isolated island regions in a semiconductor substrate by selective etching and oxidation and devices formed therefrom Reach-through isolation silicon-on-insulator device Method of making a high-density DRAM structure on SOI High-density DRAM structure on soi Patent #: 5528062 InventorApplicationNo. 706230 filed on 09/04/1996US Classes:438/412, Semiconductor islands formed upon insulating substrate or layer (e.g., mesa isolation, etc.)257/E21.258, Using masks (EPO)257/E21.554, Using auxiliary pillars in recessed region, e.g., to form LOCOS over extended areas (EPO)257/E21.564SOI together with lateral isolation, e.g., using local oxidation of silicon, or dielectric or polycrystalline material refilled trench or air gap isolation regions, e.g., completely isolated semiconductor islands (EPO)ExaminersPrimary: Dang, TrungAttorney, Agent or FirmInternational ClassH01L 021/76AbstractUsing sub-micron technology, silicon on insulator (SOI) rows and islands are formed in a silicon substrate. Trenches are directionally-etched in the silicon substrate, leaving rows of silicon between the trenches. Silicon nitride is then deposited over the trenches, extending partly down the sides of the trenches. An isotropic chemical etch is then used to partially undercut narrow rows of silicon in the substrate. A subsequent oxidation step fully undercuts the rows of silicon, isolating the silicon rows from adjacent active areas. Devices, such as transistors for CMOS and DRAMs, are then formed in active areas, wherein the active areas are defined on the silicon rows by LOCal Oxidation of Silicon (LOCOS). | |
