Method of parallel processing for avoiding competition control problems and data up dating problems common in shared memory systems
Data processing system with search processor which initiates searching in response to predetermined disk read and write commands
Arrayed disk drive system and method
On-line reconstruction of a failed redundant array system
Dynamic task allocation in a multi-processor system employing distributed control processors and distributed arithmetic processors
Using time stamps to correlate data processing event times in connected data processing units Patent #: 5471631
ApplicationNo. 415157 filed on 03/31/1995
US Classes:711/114, Arrayed (e.g., RAIDs)711/5, For multiple memory modules (e.g., banks, interleaved memory)711/112, Direct access storage device (DASD)711/113, Caching711/202, Address mapping (e.g., conversion, translation)711/206, Translation tables (e.g., segment and page table or map)711/209, Including plural logical address spaces, pages, segments, blocks714/764Error correct and restore
ExaminersPrimary: Swann, Tod R.
Assistant: Tran, Denise
Attorney, Agent or Firm
International ClassG06F 011/00
AbstractA RAID-compatible data storage system which allows incremental increases in storage capacity at a cost that is proportional to the increase in capacity. The system does not require changes to the host system. The control and interface functions previously performed by a single (or redundant) central data storage device controller are distributed among a number of modular control units (MCUs). Each MCU is preferably physically coupled to a data storage device to form a basic, low-cost integrated storage node. One of two bus ports interfaces an MCU with the host computer on a host bus, and the other bus port interfaces an MCU with one or more data storage devices coupled to the MCU by a data storage device bus. The serial interface ports provide a means by which each of the MCUs may communicate with each other MCU to facilitate the implementation of a memory array architecture. The entire data storage array may appear as a single device capable of responding to a single identification number on the host bus, or may appear as a number of independent devices. A controlling MCU receives a command and notifies the other MCUs that are involved in a read or write operation. Control of the host bus is transferred from one MCU to the next MCU in sequence so that the data is received by the host computer, or written to each data storage device, in the proper order.