Reconfigurable torus network having switches between all adjacent processor elements for statically or dynamically splitting the network into a plurality of subsystems
July 18, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMultiprocessor computer system for executing a splittable algorithm, notably a recursive algorithm Self configuring bus structure for computer network Reconfigurable high-speed integrated local network Reconfigurable local area network Programmable pipelined image processor Method and apparatus for interconnecting processors in a hyper-dimensional array Array processor and control method thereof Method for controlling propogation of data and transform through memory-linked wavefront array processor Reconfigurable signal processor Regenerative repeater InventorsApplicationNo. 683140 filed on 07/18/1996US Classes:710/316, Path selecting switch712/15ReconfiguringExaminersPrimary: An, Meng-Ai T.Attorney, Agent or FirmForeign Patent References
International ClassG06F 015/16Foreign Application Priority Data1993-03-31 JPAbstractAn n-dimensional torus network-based parallel computer, n being an integer greater than 1, is folded n times with the results of folding embedded in an n-dimensional layer for connection with an interleave connecting unit. Four-terminal switches or switch units are placed at the folding positions. The switching units are changed so that any two of the four terminals are linked together. This permits the torus network to be split into subtorus networks or subtori. The subtori can be integrated into the original torus network whereby the reconfiguration of the torus network is realized. The switches are changed over by the switching unit in either a static mode or a dynamic mode. In the static mode, only the system side is allowed to change over the switches. In the dynamic mode, users are allowed to transmit a message to cause the switching unit to change over the switches. By connecting a communications path between the switches, the communication distance between distant processor elements can be reduced, permitting high-speed communication. This permits high-speed global calculations and broadcast processing. | |
