Integrated circuits comprising interconnecting plugs
August 7, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor device with a wiring layer having good step coverage for contact holes Method of making a stacked capacitor DRAM cell Process to fabricate a double ring stacked cell structure 5118640 Stacked capacitor dram cell and method of fabricating Process for formation of cells having self-aligned capacitor contacts, and structure thereof Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing Method of manufacturing DRAM cell having a cup shaped polysilicon storage electrode Method of manufacturing field effect transistor having a multilayer interconnection layer therein with tapered sidewall insulation Method of forming a bit line over capacitor array of memory cells InventorsApplicationNo. 700320 filed on 08/07/1996US Classes:257/296, Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell)257/309, With increased effective electrode surface area (e.g., tortuous path, corrugated, or textured electrodes)257/753, With adhesion promoting means (e.g., layer of material) to promote adhesion of contact to an insulating layer257/774, Via (interconnection hole) shape257/915, WITH TITANIUM NITRIDE PORTION OR REGION257/E21.008, Of capacitor (EPO)257/E21.575, Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (EPO)257/E21.577, By forming via holes (EPO)257/E21.589, By forming conductive members before deposition of protective insulating material, e.g., pillars, studs (EPO)257/E21.646, Dynamic random access memory structures (DRAM) (EPO)257/E21.648, Capacitor stacked over transfer transis tor (EPO)257/E23.019, Consisting of layered constructions comprising conductive layers and insulating layers, e.g., planar contacts (EPO)257/E27.081, Including field-effect component (EPO)257/E27.086Storage electrode stacked over the transistorExaminersPrimary: Thomas, TomAssistant: Hardy, David B. Attorney, Agent or FirmForeign Patent References
International ClassesH01L 027/108H01L 029/41 AbstractA semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the active areas; g) a bit line plug extending through the insulating layer and electrically interconnecting the bit line with the other active area, the bit line plug comprising an electrically conductive annular ring. Integrated circuitry, beyond memory devices, utilizing an annular interconnection ring are also disclosed. Such constructions having additional radially inward insulating annular rings and conductive rings are also disclosed. A method of forming a bit line over capacitor array of memory cells having such rings is also disclosed.Other References
Field of SearchWITH TITANIUM NITRIDE PORTION OR REGIONOf specified configuration Via (interconnection hole) shape Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell) Capacitor for signal storage in combination with non-volatile storage means With adhesion promoting means (e.g., layer of material) to promote adhesion of contact to an insulating layer TRANSMISSION LINE LEAD (E.G., STRIPLINE, COAX, ETC.) | |
