Digital signal processor configured for multiprocessing
November 4, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMultiple microprocessor intercommunication arrangement Multiprocessor computer system utilizing a tapped delay line instruction bus Method and apparatus for parallel processing of digital signals using multiple independent signal processors Multiprocessor system employing dynamically programmable processing elements controlled by a master processor Multiprocessing system having dynamically allocated local/global storage and including interleaving transformation circuit for transforming real addresses to corresponding absolute address of the storage Time multiplexed system for tightly coupling pipelined processors to separate shared instruction and data storage units Synchronized parallel processing with shared memory Data processing device with improved direct memory access 5117350 Multiprocessor system having distributed shared resources and dynamic and selective global data replication InventorsAssigneeApplicationNo. 317744 filed on 10/04/1994US Classes:712/36, Application specific711/153, Shared memory partitioning712/34Including coprocessorExaminersPrimary: Coleman, EricAttorney, Agent or FirmForeign Patent References
International ClassG06F 013/00AbstractA monolithic digital signal processor includes a core processor for performing digital signal computations, an I/O processor for controlling external access to and from the digital signal processor through an external port, first and second memory banks for storing instructions and data for the digital signal computations, and first and second buses interconnecting the core processor, the I/O processor and the memory banks. The core processor and the I/O processor access the memory banks on the first bus without interference on different clock phases of a clock cycle. The internal memory and the I/O processor of the digital signal processor are assigned to a region of a global memory space, which facilitates multiprocessing configurations. In a multiprocessor system, each digital signal processor is assigned a processor ID. The digital signal processor includes a bus arbitration circuit for controlling access to an external bus through the external port. The digital signal processor may include one or more serial ports and one or more link ports for point-to-point communication with external devices. A DMA controller controls DMA transfers through the external port, the serial ports and the link ports.Other References
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