Data communication adapter and data communication terminal apparatus for performing data transmission and reception between terminals

Patent 5682552 Issued on October 28, 1997. Estimated Expiration Date:

October 28, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

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Inventors

Assignee

Application

No. 248529 filed on 05/24/1994

US Classes:

710/52Input/Output data buffering

Examiners

Primary: Treat, William M.

Attorney, Agent or Firm

Antonelli, Terry, Stout & Kraus, LLP.

Foreign Patent References

0226975 EP. 12/13/1986
8603607 WO. 06/13/1986

International Class

G06F 013/40

Foreign Application Priority Data

1989-06-30 JP

Abstract

In a data communication adapter apparatus for a digital data communication connected between a signal transmission path for transmitting both receive data and transmit data, and a host processor unit for producing frame data to output the frame data therefrom, an internal host bus is newly employed in the data communication apparatus irrelevant to the employment of a CPU dedicated bus, and the transmission/reception data generated and interpreted by the host processor is transferred via the internal host bus, a bus interface, and a system data bus between a transmission memory or a reception memory and a buffer memory. Furthermore, a reception memory (host dedicated reception memory) for storing only the reception data to be interpreted by the host processor is separately provided with another reception memory (CPU dedicated reception memory) for storing only the reception data to be interpreted by a CPU, one reception data to be interpreted by the CPU is once transferred from the transmission/reception control unit to the CPU dedicated memory and thereafter read out via the CPU dedicated bus under the control of the CPU, and the other reception data to be interpreted by the host processor is one stored in the host dedicated reception memory and then read out via the internal host bus and bus interface under the control of the host processor.

Other References

Wescon Technical Papers, "IEEE 802.3 Chipset Simplifies LAN Interface", by R.V. Balakrishnan, Oct. 30 to Nov. 2, 1984, Anaheim, California, Los Angeles, U.S.