Scoreboard table for a counterflow pipeline processor with instruction packages and result packages
Patent 5682493 Issued on October 28, 1997. Estimated Expiration Date: 
August 26, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
August 26, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesCombined write-operand queue and read-after-write dependency scoreboard Central processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution Multiprocessor coupling system with integrated compile and run time scheduling for parallelism Patent #: 5574939 InventorsApplicationNo. 520281 filed on 08/26/1995US Classes:712/217, Scoreboarding, reservation station, or aliasing712/41, RISC712/42, Operation712/218Commitment control or register bypassExaminersPrimary: Lall, Parshotam S.Assistant: Vu, Viet D. Attorney, Agent or FirmInternational ClassG06F 009/38AbstractA counterflow pipeline having a scoreboard table and a register file is disclosed. In the counterflow pipeline, information flows in two directions. Instructions flow up the pipeline during execution. The results from previous instructions flow down the same pipeline. As an instruction meets a result that is needed by that instruction, that result is garnered. The scoreboard table maintains a record of the registers values that are being recomputed in the counterflow pipeline at any given point in time. When a new instruction enters the counterflow pipeline, the register values it needs are compared to the record of register values being recomputed or otherwise stored in the scoreboard table. If a match occurs, the source value is not fetched from the register file. Rather, the needed source value is garnered in the counter flow pipeline. By this procedure, the number of times the register file need be accessed is significantly reduced. | |
