Method and system for testing memory programming devices
March 17, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProcess of performing burn-in and parallel functional testing of integrated circuit memories in an environmental chamber Personal computer-based dynamic burn-in system Flash memory circuit and method of operation Flash-type nonvolatile semiconductor memory having precise erasing levels Semiconductor memory Architecture of circuitry for generating test mode signals Apparatus and method to test random access memories for a plurality of possible types of faults External tester control for flash memory Method and apparatus for improving data failure rate testing for memory arrays Method for reliably storing non-data fields in a flash EEPROM memory array InventorsAssigneeApplicationNo. 407103 filed on 03/17/1995US Classes:714/25, Fault locating (i.e., diagnosis or testing)714/45, Output recording (e.g., signature or trace)714/46, Operator interface for diagnosing or testing714/47Performance monitoring for fault avoidanceExaminersPrimary: Beausoliel, Robert W. Jr.Assistant: Wright, Norman M. Attorney, Agent or FirmInternational ClassG06F 011/00AbstractA novel system and method for testing semiconductor devices has a pattern generator implementing a test signal algorithm uniquely coupled with a recording system which is an individual hardware system for each device under test. The improved pattern generator and recording system functions in conjunction with a system designed to perform parallel test and burn-in of semiconductor devices, such as the Aehr Test MTX System. The MTX can functionally test large quantities of semiconductor devices in parallel. It can also compensate for the appropriate round trip delay value for each chip select state for each device under test. This system of testing provides an effective and practical method for reducing overall test cost without sacrificing quality.Other References
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