Apparatus and method for switching asynchronous clock signals
November 5, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMultiple clock switching circuit Dynamic switching circuit for multiple asynchronous clock sources Glitch free clock select Clock selection circuit for selecting one of a plurality of clock pulse signals Multiple external asynchronous triggers circuit Clock switching apparatus and method for computer systems Circuit for glitch-free switching of asynchronous clock sources Circuit for synchronous, glitch-free clock switching Method and apparatus for providing an uninterrupted clock signal in a data processing system Patent #: 5371764 InventorAssigneeApplicationNo. 744121 filed on 11/05/1996US Classes:375/354, SYNCHRONIZERS327/145, Having different frequencies340/825.2, Synchronizing713/501Multiple or variable intervals or frequenciesExaminersPrimary: Chin, WellingtonAssistant: Luther, William Attorney, Agent or FirmForeign Patent References
International ClassH04L 007/00Foreign Application Priority Data1994-02-23 GBAbstractWithin a data processing system having two alternative clock signals of different frequencies (fclk, mclk) it is necessary to provide a mechanism for switching between the clock signals. When switching from the fast clock (fclk) to the slow clock (mclk), the system adopts the slow clock from the first falling edge (ffe) after a processing delay (PD) associated with the decision as to whether or not to change clocks. This processing delay can be greater than one half of a cycle of the fast clock. In contrast, when switching from the slow clock to the fast clock, the system adopts the fast clock from the first rising edge (fre) following the processing delay. Thus, a system is provided in which differing strategies for synchronization are adopted depending upon the direction of change of the clock signal.Other References
Field of SearchNetwork synchronizing more than two stationsSynchronization failure prevention Phase displacement, slip or jitter correction SYNCHRONIZERS Self-synchronizing signal (self-clocking codes, etc.) Synchronizing Having different frequencies Using multiple clocks Including field-effect transistor Having selection between plural continuous waveforms CLOCKING OR SYNCHRONIZING OF LOGIC STAGES OR GATES Two or more clocks (e.g., phase clocking, etc.) Selectively connected to common output or oscillator substitution Synchronizing | |
