Apparatus to dynamically control the out-of-order execution of load/store instructions in a processor capable of dispatchng, issuing and executing multiple instructions in a single processor cycle
May 12, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of storing data in a memory of a data processing system Dual pipe cache memory with out-of-order issue capability Method and apparatus employing lookahead to reduce memory bank contention for decoupled operand references Intelligent storage manager for data storage apparatus having simulation capability Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts Method an apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency Cache memory system and method with multiple hashing functions and hash control storage Patent #: 5530958 InventorsApplicationNo. 440025 filed on 05/12/1995US Classes:712/216, DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION712/218Commitment control or register bypassExaminersPrimary: Treat, William M.Assistant: Coulter, Kenneth R. Attorney, Agent or FirmInternational ClassG06F 009/38AbstractAn apparatus to dynamically controls the out-of-order execution of load/store instructions by detecting a store violation condition and avoiding the penalty of a pipeline recovery process. The apparatus permits a load and store instruction to issue and execute out of order and incorporates a unique store barrier cache which is used to dynamically predict whether or not a store violation condition is likely to occur and, if so, to restrict the issue of instructions to the load/store unit until the store instruction has been executed and it is once again safe to proceed with out-of-order execution. The method implemented by the apparatus delivers performance within one percent of theoretically possible with apriori knowledge of load and store addresses. | |
