Digital fail operational automatic flight control system utilizing redundant dissimilar data processing
Fault-tolerant computer with three independently clocked processors asynchronously executing identical code that are synchronized upon each voted access to two memory modules
Integrated fault-tolerant air data inertial reference system
Asynchronous TMR processing system
Skewed axis inertial sensor assembly
Method and apparatus for implementing a databus voter to select flight command signals from one of several redundant asynchronous digital primary flight computers Patent #: 5515282
ApplicationNo. 532949 filed on 09/22/1995
US Classes:714/10, Of processor701/4, Altitude or attitude control or indication701/62, Fail-safe control (e.g., preventing a gear shift)701/200, NAVIGATION714/11Concurrent, redundantly operating processors
ExaminersPrimary: Beausoliel, Robert W. Jr.
Assistant: Le, Dieu-Minh
Attorney, Agent or Firm
Foreign Patent References
International ClassG06F 011/00
AbstractDisclosed is a fault-tolerant and/or fail-safe information processing system architecture for handling information from a plurality of independent subsystems which provide information related to selected input quantities, and which includes a plurality of redundant information processors for deriving specific processor output data as a function of the selected subsystem input quantities.